static int s3c_pwm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct s3c_chip *s3c;
unsigned long flags;
unsigned long tcon;
unsigned int id = pdev->id;
int ret;
if (id == 4) {
dev_err(dev, "TIMER4 is currently not supported\n");
return -ENXIO;
}
s3c = devm_kzalloc(&pdev->dev, sizeof(*s3c), GFP_KERNEL);
if (s3c == NULL) {
dev_err(dev, "failed to allocate pwm_device\n");
return -ENOMEM;
}
/* calculate base of control bits in TCON */
s3c->tcon_base = id == 0 ? 0 : (id * 4) + 4;
s3c->chip.dev = &pdev->dev;
s3c->chip.ops = &s3c_pwm_ops;
s3c->chip.base = -1;
s3c->chip.npwm = 1;
s3c->clk = devm_clk_get(dev, "pwm-tin");
if (IS_ERR(s3c->clk)) {
dev_err(dev, "failed to get pwm tin clk\n");
return PTR_ERR(s3c->clk);
}
s3c->clk_div = devm_clk_get(dev, "pwm-tdiv");
if (IS_ERR(s3c->clk_div)) {
dev_err(dev, "failed to get pwm tdiv clk\n");
return PTR_ERR(s3c->clk_div);
}
clk_enable(s3c->clk);
clk_enable(s3c->clk_div);
local_irq_save(flags);
tcon = __raw_readl(S3C2410_TCON);
tcon |= pwm_tcon_invert(s3c);
__raw_writel(tcon, S3C2410_TCON);
local_irq_restore(flags);
ret = pwmchip_add(&s3c->chip);
if (ret < 0) {
dev_err(dev, "failed to register pwm\n");
goto err_clk_tdiv;
}
pwm_dbg(s3c, "config bits %02x\n",
(__raw_readl(S3C2410_TCON) >> s3c->tcon_base) & 0x0f);
dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n",
clk_get_rate(s3c->clk),
clk_get_rate(s3c->clk_div),
pwm_is_tdiv(s3c) ? "div" : "ext", s3c->tcon_base);
platform_set_drvdata(pdev, s3c);
return 0;
err_clk_tdiv:
clk_disable(s3c->clk_div);
clk_disable(s3c->clk);
return ret;
}
static int s3c_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
int duty_ns, int period_ns)
{
struct s3c_chip *s3c = to_s3c_chip(chip);
struct s3c_pwm_device *s3c_pwm = pwm_get_chip_data(pwm);
void __iomem *reg_base = s3c->reg_base;
unsigned long tin_rate;
unsigned long tin_ns;
unsigned long period;
unsigned long flags;
unsigned long tcon;
unsigned long tcnt;
long tcmp;
enum duty_cycle duty_cycle;
unsigned int id = pwm->pwm;
/* We currently avoid using 64bit arithmetic by using the
* fact that anything faster than 1Hz is easily representable
* by 32bits. */
if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
return -ERANGE;
if (duty_ns > period_ns)
return -EINVAL;
if (period_ns == s3c_pwm->period_ns &&
duty_ns == s3c_pwm->duty_ns)
return 0;
period = NS_IN_HZ / period_ns;
/* Check to see if we are changing the clock rate of the PWM */
if (s3c_pwm->period_ns != period_ns && pwm_is_tdiv(s3c_pwm)) {
tin_rate = pwm_calc_tin(pwm, period);
clk_set_rate(s3c_pwm->clk_div, tin_rate);
tin_rate = clk_get_rate(s3c_pwm->clk_div);
s3c_pwm->period_ns = period_ns;
pwm_dbg(s3c, "tin_rate=%lu\n", tin_rate);
} else {
tin_rate = clk_get_rate(s3c_pwm->clk_tin);
}
if(!tin_rate)
return -EFAULT;
/* Note, counters count down */
tin_ns = NS_IN_HZ / tin_rate;
tcnt = DIV_ROUND_CLOSEST(period_ns, tin_ns);
tcmp = DIV_ROUND_CLOSEST(duty_ns, tin_ns);
if (tcnt <= 1) {
/* Too small to generate a pulse */
return -ERANGE;
}
pwm_dbg(s3c, "duty_ns=%d, period_ns=%d (%lu)\n",
duty_ns, period_ns, period);
if (tcmp == 0)
duty_cycle = DUTY_CYCLE_ZERO;
else if (tcmp == tcnt)
duty_cycle = DUTY_CYCLE_FULL;
else
duty_cycle = DUTY_CYCLE_PULSE;
tcmp = tcnt - tcmp;
/* the pwm hw only checks the compare register after a decrement,
so the pin never toggles if tcmp = tcnt */
if (tcmp == tcnt)
tcmp--;
/*
* PWM counts 1 hidden tick at the end of each period on S3C64XX and
* EXYNOS series, so tcmp and tcnt should be subtracted 1.
*/
if (!pwm_is_s3c24xx(s3c)) {
tcnt--;
/*
* tcmp can be -1. It appears 100% duty cycle and PWM never
* toggles when TCMPB is set to 0xFFFFFFFF (-1).
*/
tcmp--;
}
pwm_dbg(s3c, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
/* Update the PWM register block. */
spin_lock_irqsave(&pwm_spinlock, flags);
__raw_writel(tcmp, reg_base + REG_TCMPB(id));
__raw_writel(tcnt, reg_base + REG_TCNTB(id));
if (pwm_is_s3c24xx(s3c)) {
tcon = __raw_readl(reg_base + REG_TCON);
tcon |= pwm_tcon_manulupdate(s3c_pwm);
tcon |= pwm_tcon_autoreload(s3c_pwm);
__raw_writel(tcon, reg_base + REG_TCON);
tcon &= ~pwm_tcon_manulupdate(s3c_pwm);
__raw_writel(tcon, reg_base + REG_TCON);
} else {
tcon = __raw_readl(reg_base + REG_TCON);
if (s3c_pwm->running == 1 &&
tcon & pwm_tcon_start(s3c_pwm) &&
s3c_pwm->duty_cycle != duty_cycle) {
if (duty_cycle == DUTY_CYCLE_ZERO) {
tcon |= pwm_tcon_manulupdate(s3c_pwm);
__raw_writel(tcon, reg_base + REG_TCON);
tcon &= ~pwm_tcon_manulupdate(s3c_pwm);
tcon &= ~pwm_tcon_autoreload(s3c_pwm);
} else {
tcon |= pwm_tcon_autoreload(s3c_pwm);
}
__raw_writel(tcon, reg_base + REG_TCON);
}
}
s3c_pwm->duty_ns = duty_ns;
s3c_pwm->period_ns = period_ns;
s3c_pwm->duty_cycle = duty_cycle;
spin_unlock_irqrestore(&pwm_spinlock, flags);
return 0;
}
static int s3c_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
int duty_ns, int period_ns)
{
struct s3c_chip *s3c = to_s3c_chip(chip);
unsigned long tin_rate;
unsigned long tin_ns;
unsigned long period;
unsigned long flags;
unsigned long tcon;
unsigned long tcnt;
long tcmp;
/* We currently avoid using 64bit arithmetic by using the
* fact that anything faster than 1Hz is easily representable
* by 32bits. */
if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
return -ERANGE;
if (duty_ns > period_ns)
return -EINVAL;
if (period_ns == s3c->period_ns &&
duty_ns == s3c->duty_ns)
return 0;
/* The TCMP and TCNT can be read without a lock, they're not
* shared between the timers. */
tcmp = __raw_readl(S3C2410_TCMPB(s3c->pwm_id));
tcnt = __raw_readl(S3C2410_TCNTB(s3c->pwm_id));
period = NS_IN_HZ / period_ns;
pwm_dbg(s3c, "duty_ns=%d, period_ns=%d (%lu)\n",
duty_ns, period_ns, period);
/* Check to see if we are changing the clock rate of the PWM */
if (s3c->period_ns != period_ns) {
if (pwm_is_tdiv(s3c)) {
tin_rate = pwm_calc_tin(s3c, period);
clk_set_rate(s3c->clk_div, tin_rate);
} else
tin_rate = clk_get_rate(s3c->clk);
s3c->period_ns = period_ns;
pwm_dbg(s3c, "tin_rate=%lu\n", tin_rate);
tin_ns = NS_IN_HZ / tin_rate;
tcnt = period_ns / tin_ns;
} else
tin_ns = NS_IN_HZ / clk_get_rate(s3c->clk);
/* Note, counters count down */
tcmp = duty_ns / tin_ns;
tcmp = tcnt - tcmp;
/* the pwm hw only checks the compare register after a decrement,
so the pin never toggles if tcmp = tcnt */
if (tcmp == tcnt)
tcmp--;
pwm_dbg(s3c, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
if (tcmp < 0)
tcmp = 0;
/* Update the PWM register block. */
local_irq_save(flags);
__raw_writel(tcmp, S3C2410_TCMPB(s3c->pwm_id));
__raw_writel(tcnt, S3C2410_TCNTB(s3c->pwm_id));
tcon = __raw_readl(S3C2410_TCON);
tcon |= pwm_tcon_manulupdate(s3c);
tcon |= pwm_tcon_autoreload(s3c);
__raw_writel(tcon, S3C2410_TCON);
tcon &= ~pwm_tcon_manulupdate(s3c);
__raw_writel(tcon, S3C2410_TCON);
local_irq_restore(flags);
return 0;
}