void set_kpd_pmic_mode() { unsigned int a,c; a = pwrap_read(0x0502,&c); if(a != 0) print("kpd write fail, addr: 0x0502\n"); //print("kpd read addr: 0x0502: data:0x%x\n", c); c=c&0xFFFE; a = pwrap_write(0x0502,c); if(a != 0) print("kpd write fail, addr: 0x0502\n"); mtk_kpd_gpio_set(); int rel = 0; rel = pmic_config_interface(WRP_CKPDN,0x0,PMIC_RG_WRP_KP_PDN_MASK, PMIC_RG_WRP_KP_PDN_SHIFT); if(rel != 0){ print("kpd set clock register fail!\n"); } *(volatile u16 *)(KP_PMIC) = 0x1; print("kpd register for pmic set!\n"); return; }
// pmic wrap read and write func static unsigned int vibr_pmic_pwrap_read(U32 addr) { U32 val =0; pwrap_read(addr, &val); return val; }
// pmic wrap read and write func unsigned int vibr_pmic_pwrap_read(U32 addr) { U32 val =0; pwrap_read(addr, &val); //ACCDET_DEBUG("[Accdet]wrap write func addr=0x%x, val=0x%x\n", addr, val); return val; }
uint32 Ana_Get_Reg(uint32 offset) { /* get pmic register */ int ret = 0; uint32 Rdata = 0; #ifdef AUDIO_USING_WRAP_DRIVER ret = pwrap_read(offset, &Rdata); #endif pr_debug("Ana_Get_Reg offset= 0x%x Rdata = 0x%x ret = %d\n", offset, Rdata, ret); return Rdata; }
uint32 Ana_Get_Reg(uint32 offset) { // get pmic register int ret = 0; uint32 Rdata = 0; #ifdef AUDIO_USING_WRAP_DRIVER ret = pwrap_read(offset, &Rdata); #endif PRINTK_ANA_REG ("Ana_Get_Reg offset= 0x%x Rdata = 0x%x ret = %d\n",offset,Rdata,ret); return Rdata; }
/* static bool spm_set_suspend_pcm_ver(u32 *suspend_flags) { u32 flag; flag = *suspend_flags; if(mt_get_clk_mem_sel()==MEMPLL3PLL) { __spm_suspend.pcmdesc = &suspend_pcm_3pll; flag |= SPM_VCORE_DVS_DIS; } else if(mt_get_clk_mem_sel()==MEMPLL1PLL) { __spm_suspend.pcmdesc = &suspend_pcm_1pll; flag &= ~SPM_VCORE_DVS_DIS; } else return false; *suspend_flags = flag; return true; } */ static void spm_suspend_pre_process(struct pwr_ctrl *pwrctrl) { #if 0 u32 rdata1 = 0, rdata2 = 0; #endif /* set PMIC WRAP table for suspend power control */ mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_SUSPEND); spm_i2c_control(I2C_CHANNEL, 1); #if 0 /* for infra pdn (emi driving) */ spm_write(0xF0004000, spm_read(0xF0004000) | (1 << 24)); /* MEMPLL control for SPM */ spm_write(0xF000F5C8, 0x3010F030); spm_write(0xF000F5CC, 0x50101010); #endif //spm_write(0xF0001070 , spm_read(0xF0001070) | (1 << 21)); // 26:26 enable //spm_write(0xF0000204 , spm_read(0xF0000204) | (1 << 0)); // BUS 26MHz enable //spm_write(0xF0001108 , 0x0); #ifdef CONFIG_MD32_SUPPORT //spm_write(MD32_BASE+0x2C, (spm_read(MD32_BASE+0x2C) & ~0xFFFF) | 0xcafe); #endif #if 0 pwrap_read(0x2c2, &rdata1); pwrap_write(0x2c2, 0x0123); pwrap_read(0x2c2, &rdata2); if(rdata2 != 0x0123) { spm_crit2("suspend pmic wrapper 0x2c2, rdata1 = 0x%x, rdata2 = 0x%x\n", rdata1, rdata2); BUG(); } #endif }
static void spm_suspend_post_process(struct pwr_ctrl *pwrctrl) { #if 0 u32 rdata1 = 0, rdata2 = 0; pwrap_read(0x2c2, &rdata1); pwrap_write(0x2c2, 0x3210); pwrap_read(0x2c2, &rdata2); if(rdata2 != 0x3210) { spm_crit2("resume pmic wrapper 0x2c2, rdata1 = 0x%x, rdata2 = 0x%x\n", rdata1, rdata2); BUG(); } #endif #ifdef CONFIG_MD32_SUPPORT //spm_write(MD32_BASE+0x2C, spm_read(MD32_BASE+0x2C) & ~0xFFFF); #endif /* set PMIC WRAP table for normal power control */ mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_NORMAL); spm_i2c_control(I2C_CHANNEL, 0); }
void set_kpd_pmic_mode(void) { unsigned int a,c; a = pwrap_read(0x0040,&c); if(a != 0) printf("kpd write fail, addr: 0x0502\n"); printf("kpd read addr: 0x0502: data:0x%x\n", c); c = c&0xFFFE;//0x4000; a = pwrap_write(0x0040,c); if(a != 0) printf("kpd write fail, addr: 0x0502\n"); //#ifdef MT65XX_PMIC_RST_KEY // pmic_config_interface(GPIO_SMT_CON3,0x01, PMIC_RG_HOMEKEY_PUEN_MASK, PMIC_RG_HOMEKEY_PUEN_SHIFT);//pull up homekey pin of PMIC for 89 project //#endif return; }
void set_kpd_pmic_mode() { unsigned int a,c; a = pwrap_read(0x0502,&c); if(a != 0) printf("kpd write fail, addr: 0x0502\n"); printf("kpd read addr: 0x0502: data:0x%x\n", c); c = c&0xFFFE;//0x4000; a = pwrap_write(0x0502,c); if(a != 0) printf("kpd write fail, addr: 0x0502\n"); #ifdef MT65XX_PMIC_RST_KEY pmic_config_interface(GPIO_SMT_CON3,0x01, PMIC_RG_HOMEKEY_PUEN_MASK, PMIC_RG_HOMEKEY_PUEN_SHIFT);//pull up homekey pin of PMIC for 89 project #endif mt65xx_reg_sync_writew(0x1, KP_PMIC); printf("kpd register for pmic set!\n"); return; }
static U16 gs6323_pmic_read(U16 addr) { U32 rdata=0; pwrap_read((U32)addr, &rdata); return (U16)rdata; }