void sharpsl_pm_pxa_init(void)
{
pxa_gpio_mode(sharpsl_pm.machinfo->gpio_acin | GPIO_IN);
pxa_gpio_mode(sharpsl_pm.machinfo->gpio_batfull | GPIO_IN);
pxa_gpio_mode(sharpsl_pm.machinfo->gpio_batlock | GPIO_IN);
/* Register interrupt handlers */
if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED, "AC Input Detect", sharpsl_ac_isr)) {
dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin));
}
else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin),IRQ_TYPE_EDGE_BOTH);
if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED, "Battery Cover", sharpsl_fatal_isr)) {
dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock));
}
else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock),IRQ_TYPE_EDGE_FALLING);
if (sharpsl_pm.machinfo->gpio_fatal) {
if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED, "Fatal Battery", sharpsl_fatal_isr)) {
dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal));
}
else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal),IRQ_TYPE_EDGE_FALLING);
}
if (sharpsl_pm.machinfo->batfull_irq)
{
/* Register interrupt handler. */
if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED, "CO", sharpsl_chrg_full_isr)) {
dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull));
}
else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull),IRQ_TYPE_EDGE_RISING);
}
}
static void corgi_charger_init(void)
{
pxa_gpio_mode(CORGI_GPIO_ADC_TEMP_ON | GPIO_OUT);
pxa_gpio_mode(CORGI_GPIO_CHRG_ON | GPIO_OUT);
pxa_gpio_mode(CORGI_GPIO_CHRG_UKN | GPIO_OUT);
pxa_gpio_mode(CORGI_GPIO_KEY_INT | GPIO_IN);
}
static void __init poodle_init(void)
{
int ret = 0;
pm_power_off = poodle_poweroff;
arm_pm_restart = poodle_restart;
/* setup sleep mode values */
PWER = 0x00000002;
PFER = 0x00000000;
PRER = 0x00000002;
PGSR0 = 0x00008000;
PGSR1 = 0x003F0202;
PGSR2 = 0x0001C000;
PCFR |= PCFR_OPDE;
/* cpu initialize */
/* Pgsr Register */
PGSR0 = 0x0146dd80;
PGSR1 = 0x03bf0890;
PGSR2 = 0x0001c000;
/* Alternate Register */
GAFR0_L = 0x01001000;
GAFR0_U = 0x591a8010;
GAFR1_L = 0x900a8451;
GAFR1_U = 0xaaa5aaaa;
GAFR2_L = 0x8aaaaaaa;
GAFR2_U = 0x00000002;
/* Direction Register */
GPDR0 = 0xd3f0904c;
GPDR1 = 0xfcffb7d3;
GPDR2 = 0x0001ffff;
/* Output Register */
GPCR0 = 0x00000000;
GPCR1 = 0x00000000;
GPCR2 = 0x00000000;
GPSR0 = 0x00400000;
GPSR1 = 0x00000000;
GPSR2 = 0x00000000;
set_pxa_fb_parent(&poodle_locomo_device.dev);
set_pxa_fb_info(&poodle_fb_info);
pxa_gpio_mode(POODLE_GPIO_USB_PULLUP | GPIO_OUT);
pxa_gpio_mode(POODLE_GPIO_IR_ON | GPIO_OUT);
pxa_set_udc_info(&udc_info);
pxa_set_mci_info(&poodle_mci_platform_data);
pxa_set_ficp_info(&poodle_ficp_platform_data);
platform_scoop_config = &poodle_pcmcia_config;
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
if (ret) {
printk(KERN_WARNING "poodle: Unable to register LoCoMo device\n");
}
corgi_ssp_set_machinfo(&poodle_ssp_machinfo);
}
static int mst_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
{
/*
* Setup default state of GPIO outputs
* before we enable them as outputs.
*/
GPSR(GPIO48_nPOE) =
GPIO_bit(GPIO48_nPOE) |
GPIO_bit(GPIO49_nPWE) |
GPIO_bit(GPIO50_nPIOR) |
GPIO_bit(GPIO51_nPIOW) |
GPIO_bit(GPIO85_nPCE_1) |
GPIO_bit(GPIO54_nPCE_2);
pxa_gpio_mode(GPIO48_nPOE_MD);
pxa_gpio_mode(GPIO49_nPWE_MD);
pxa_gpio_mode(GPIO50_nPIOR_MD);
pxa_gpio_mode(GPIO51_nPIOW_MD);
pxa_gpio_mode(GPIO85_nPCE_1_MD);
pxa_gpio_mode(GPIO54_nPCE_2_MD);
pxa_gpio_mode(GPIO79_pSKTSEL_MD);
pxa_gpio_mode(GPIO55_nPREG_MD);
pxa_gpio_mode(GPIO56_nPWAIT_MD);
pxa_gpio_mode(GPIO57_nIOIS16_MD);
skt->irq = (skt->nr == 0) ? MAINSTONE_S0_IRQ : MAINSTONE_S1_IRQ;
return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
}
static int pxa2xx_ac97_probe(struct platform_device *pdev)
{
int ret;
ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
if (ret < 0)
goto err;
pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
#ifdef CONFIG_PXA27x
/* Use GPIO 113 as AC97 Reset on Bulverde */
pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
#endif
pxa_set_cken(CKEN_AC97, 1);
return 0;
err:
if (CKEN & (1 << CKEN_AC97)) {
GCR |= GCR_ACLINK_OFF;
free_irq(IRQ_AC97, NULL);
pxa_set_cken(CKEN_AC97, 0);
}
return ret;
}
static int idp_mci_init(struct device *dev, irqreturn_t (*idp_detect_int)(int, void *, struct pt_regs *), void *data)
{
/* setup GPIO for PXA25x MMC controller */
pxa_gpio_mode(GPIO6_MMCCLK_MD);
pxa_gpio_mode(GPIO8_MMCCS0_MD);
return 0;
}
static void __init colibri_init(void)
{
/* DM9000 LAN */
pxa_gpio_mode(GPIO78_nCS_2_MD);
pxa_gpio_mode(GPIO_DM9000 | GPIO_IN);
platform_add_devices(colibri_devices, ARRAY_SIZE(colibri_devices));
}
/* IRQ and GPIO's could be platform data */
static int pxa2xx_ac97_probe(struct platform_device *pdev)
{
struct pxa_ac97_data *ac97;
int ret, i;
ac97 = kzalloc(sizeof(struct pxa_ac97_data), GFP_KERNEL);
if (ac97 == NULL)
return -ENOMEM;
#ifdef CONFIG_PXA27x
/* Use GPIO 113 as AC97 Reset on Bulverde */
pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
ac97conf_clk = clk_get(&pdev->dev, "AC97CONFCLK");
if (IS_ERR(ac97conf_clk)) {
ret = -ENODEV;
goto unwind_data;
}
#endif
ac97_clk = clk_get(&pdev->dev, "AC97CLK");
if (IS_ERR(ac97_clk)) {
ret = -ENODEV;
goto unwind_data;
}
clk_enable(ac97_clk);
for (i = 0; i < ARRAY_SIZE(dais); i++) {
ac97->dai[i] = snd_soc_register_platform_dai(&dais[i],
&pdev->dev);
if (ac97->dai[i] == NULL) {
ret = -ENOMEM;
goto unwind_create;
}
}
ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97",
ac97->dai[0]);
if (ret < 0)
goto unwind_create;
pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
platform_set_drvdata(pdev, ac97);
return ret;
unwind_create:
i--;
for (; i >= 0; i--) {
snd_soc_unregister_platform_dai(ac97->dai[i]);
}
unwind_data:
kfree(ac97);
return ret;
}
static void __init hx4700_init( void )
{
#if 0 // keep for reference, from bootldr
GPSR0 = 0x0935ede7;
GPSR1 = 0xffdf40f7;
GPSR2 = 0x0173c9f6;
GPSR3 = 0x01f1e342;
GPCR0 = ~0x0935ede7;
GPCR1 = ~0xffdf40f7;
GPCR2 = ~0x0173c9f6;
GPCR3 = ~0x01f1e342;
GPDR0 = 0xda7a841c;
GPDR1 = 0x68efbf83;
GPDR2 = 0xbfbff7db;
GPDR3 = 0x007ffff5;
GAFR0_L = 0x80115554;
GAFR0_U = 0x591a8558;
GAFR1_L = 0x600a9558;
GAFR1_U = 0x0005a0aa;
GAFR2_L = 0xa0000000;
GAFR2_U = 0x00035402;
GAFR3_L = 0x00010000;
GAFR3_U = 0x00001404;
MSC0 = 0x25e225e2;
MSC1 = 0x12cc2364;
MSC2 = 0x16dc7ffc;
#endif
SET_HX4700_GPIO( ASIC3_RESET_N, 0 );
mdelay(10);
SET_HX4700_GPIO( ASIC3_RESET_N, 1 );
mdelay(10);
SET_HX4700_GPIO( EUART_RESET, 1 );
/* configure serial */
pxa_gpio_mode( GPIO_NR_HX4700_COM_RXD_MD );
pxa_gpio_mode( GPIO_NR_HX4700_COM_CTS_MD );
pxa_gpio_mode( GPIO_NR_HX4700_COM_DCD_MD );
pxa_gpio_mode( GPIO_NR_HX4700_COM_DSR_MD );
pxa_gpio_mode( GPIO_NR_HX4700_COM_RING_MD );
pxa_gpio_mode( GPIO_NR_HX4700_COM_TXD_MD );
pxa_gpio_mode( GPIO_NR_HX4700_COM_DTR_MD );
pxa_gpio_mode( GPIO_NR_HX4700_COM_RTS_MD );
/* Enable RS232 in case we'd have boot console there. In case
cable is not actually attached, it will be turned off as
soon as hx4700_serial is initialized. */
SET_HX4700_GPIO(RS232_ON, 1);
pxa_gpio_mode( GPIO_NR_HX4700_I2C_SCL_MD );
pxa_gpio_mode( GPIO_NR_HX4700_I2C_SDA_MD );
platform_add_devices( devices, ARRAY_SIZE(devices) );
pxa_set_ficp_info(&hx4700_ficp_platform_data);
led_trigger_register_shared("hx4700-radio", &hx4700_radio_trig);
}
static int gumstix_mci_init(struct device *dev, irq_handler_t detect_int,
void *data)
{
pxa_gpio_mode(GPIO6_MMCCLK_MD);
pxa_gpio_mode(GPIO53_MMCCLK_MD);
pxa_gpio_mode(GPIO8_MMCCS0_MD);
return 0;
}
/*
* Irda
*/
static void tosa_irda_transceiver_mode(struct device *dev, int mode)
{
if (mode & IR_OFF) {
reset_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_IR_POWERDWN);
pxa_gpio_mode(GPIO47_STTXD|GPIO_DFLT_LOW);
pxa_gpio_mode(GPIO47_STTXD|GPIO_OUT);
} else {
pxa_gpio_mode(GPIO47_STTXD_MD);
set_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_IR_POWERDWN);
}
}
static inline void pxa_ac97_warm_pxa27x(void)
{
gsr_bits = 0;
/* warm reset broken on Bulverde,
so manually keep AC97 reset high */
pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH);
udelay(10);
GCR |= GCR_WARM_RST;
pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
udelay(500);
}
int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
{
int ret;
if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
}
if (cpu_is_pxa27x()) {
/* Use GPIO 113 as AC97 Reset on Bulverde */
pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
if (IS_ERR(ac97conf_clk)) {
ret = PTR_ERR(ac97conf_clk);
ac97conf_clk = NULL;
goto err_conf;
}
}
ac97_clk = clk_get(&dev->dev, "AC97CLK");
if (IS_ERR(ac97_clk)) {
ret = PTR_ERR(ac97_clk);
ac97_clk = NULL;
goto err_clk;
}
ret = clk_enable(ac97_clk);
if (ret)
goto err_clk2;
ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
if (ret < 0)
goto err_irq;
return 0;
err_irq:
GCR |= GCR_ACLINK_OFF;
err_clk2:
clk_put(ac97_clk);
ac97_clk = NULL;
err_clk:
if (ac97conf_clk) {
clk_put(ac97conf_clk);
ac97conf_clk = NULL;
}
err_conf:
return ret;
}
static void __init falinux_pxa255_map_io(void)
{
pxa_map_io();
iotable_init(falinux_pxa255_io_desc, ARRAY_SIZE(falinux_pxa255_io_desc));
// FF-UART
pxa_gpio_mode(GPIO34_FFRXD_MD);
pxa_gpio_mode(GPIO39_FFTXD_MD);
// ST-UART
pxa_gpio_mode(GPIO46_STRXD_MD);
pxa_gpio_mode(GPIO47_STTXD_MD);
}
static int mainstone_ohci_init(struct device *dev)
{
/* setup Port1 GPIO pin. */
pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
/* Set the Power Control Polarity Low and Power Sense
Polarity Low to active low. */
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
return 0;
}
static int ezpxa270_mci_init(struct device *dev, irq_handler_t ezpxa270_detect_int, void *data)
{
int err;
// set GPIO
pxa_gpio_mode(GPIO32_MMCCLK_MD);
pxa_gpio_mode(GPIO112_MMCCMD_MD);
pxa_gpio_mode(GPIO92_MMCDAT0_MD);
pxa_gpio_mode(GPIO109_MMCDAT1_MD);
pxa_gpio_mode(GPIO110_MMCDAT2_MD);
pxa_gpio_mode(GPIO111_MMCDAT3_MD);
pxa_gpio_mode(GPIO1_MMC_WP_MD);
pxa_gpio_mode(GPIO10_MMC_CD_MD);
set_irq_type(GPIO_IRQ_DETECT, IRQT_FALLING); // MMC CD
err = request_irq(GPIO_IRQ_DETECT , ezpxa270_detect_int, IRQF_DISABLED,
"MMC card detect", data);
if (err) {
printk(KERN_ERR "ezpxa270_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
return -1;
}
return 0;
}
static int spitz_mci_init(struct device *dev, irq_handler_t spitz_detect_int, void *data)
{
int err;
/* setup GPIO for PXA27x MMC controller */
pxa_gpio_mode(GPIO32_MMCCLK_MD);
pxa_gpio_mode(GPIO112_MMCCMD_MD);
pxa_gpio_mode(GPIO92_MMCDAT0_MD);
pxa_gpio_mode(GPIO109_MMCDAT1_MD);
pxa_gpio_mode(GPIO110_MMCDAT2_MD);
pxa_gpio_mode(GPIO111_MMCDAT3_MD);
pxa_gpio_mode(SPITZ_GPIO_nSD_DETECT | GPIO_IN);
pxa_gpio_mode(SPITZ_GPIO_nSD_WP | GPIO_IN);
spitz_mci_platform_data.detect_delay = msecs_to_jiffies(250);
err = request_irq(SPITZ_IRQ_GPIO_nSD_DETECT, spitz_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err) {
printk(KERN_ERR "spitz_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
return -1;
}
return 0;
}
static int cmx270_mci_init(struct device *dev,
irq_handler_t cmx270_detect_int,
void *data)
{
int err;
/*
* setup GPIO for PXA27x MMC controller
*/
pxa_gpio_mode(GPIO32_MMCCLK_MD);
pxa_gpio_mode(GPIO112_MMCCMD_MD);
pxa_gpio_mode(GPIO92_MMCDAT0_MD);
pxa_gpio_mode(GPIO109_MMCDAT1_MD);
pxa_gpio_mode(GPIO110_MMCDAT2_MD);
pxa_gpio_mode(GPIO111_MMCDAT3_MD);
/* SB-X270 uses GPIO105 as SD power enable */
pxa_gpio_mode(105 | GPIO_OUT);
/* card detect IRQ on GPIO 83 */
pxa_gpio_mode(IRQ_TO_GPIO(CMX270_MMC_IRQ));
set_irq_type(CMX270_MMC_IRQ, IRQT_FALLING);
err = request_irq(CMX270_MMC_IRQ, cmx270_detect_int,
IRQF_DISABLED | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (err) {
printk(KERN_ERR "cmx270_mci_init: MMC/SD: can't"
" request MMC card detect IRQ\n");
return -1;
}
return 0;
}
static int pxa2xx_ac97_resume(struct platform_device *pdev,
struct snd_soc_cpu_dai *dai)
{
pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
#ifdef CONFIG_PXA27x
/* Use GPIO 113 as AC97 Reset on Bulverde */
pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
#endif
pxa_set_cken(CKEN2_AC97, 1);
return 0;
}
int pxa2xx_ac97_hw_resume(void)
{
if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
}
if (cpu_is_pxa27x()) {
/* Use GPIO 113 or 95 as AC97 Reset on Bulverde */
set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
}
clk_enable(ac97_clk);
return 0;
}
static int athena_ohci_init(struct device *dev)
{
/* setup Port1 GPIO pin. */
pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
/* Set the Power Control Polarity Low and Power Sense
Polarity Low to active high. */
UHCHR = (UHCHR | UHCHR_PSPL| UHCHR_SSEP2 | UHCHR_CGR) &
~(UHCHR_SSEP1 | UHCHR_PCPL | UHCHR_SSEP3 | UHCHR_SSE);
UHCRHDA &= ~UHCRHDA_NOCP;
return 0;
}
static int lubbock_mci_init(struct device *dev,
irqreturn_t (*detect_int)(int, void *, struct pt_regs *),
void *data)
{
/* setup GPIO for PXA25x MMC controller */
pxa_gpio_mode(GPIO6_MMCCLK_MD);
pxa_gpio_mode(GPIO8_MMCCS0_MD);
/* detect card insert/eject */
mmc_detect_int = detect_int;
init_timer(&mmc_timer);
mmc_timer.data = (unsigned long) data;
return request_irq(LUBBOCK_SD_IRQ, lubbock_detect_int,
SA_SAMPLE_RANDOM, "lubbock-sd-detect", data);
}
static void __init cmx270_init_irq(void)
{
pxa27x_init_irq();
cmx270_pci_init_irq();
/* Setup interrupt for dm9000 */
pxa_gpio_mode(IRQ_TO_GPIO(CMX270_ETHIRQ));
set_irq_type(CMX270_ETHIRQ, IRQT_RISING);
/* Setup interrupt for 2700G */
pxa_gpio_mode(IRQ_TO_GPIO(CMX270_GFXIRQ));
set_irq_type(CMX270_GFXIRQ, IRQT_FALLING);
}
static int
htcuniversal_phone_probe( struct platform_device *dev )
{
struct htcuniversal_phone_funcs *funcs = dev->dev.platform_data;
/* configure phone UART */
pxa_gpio_mode( GPIO_NR_HTCUNIVERSAL_PHONE_RXD_MD );
pxa_gpio_mode( GPIO_NR_HTCUNIVERSAL_PHONE_TXD_MD );
pxa_gpio_mode( GPIO_NR_HTCUNIVERSAL_PHONE_UART_CTS_MD );
pxa_gpio_mode( GPIO_NR_HTCUNIVERSAL_PHONE_UART_RTS_MD );
funcs->configure = htcuniversal_phone_configure;
return 0;
}
int pxa2xx_ac97_hw_resume(void)
{
if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
}
if (cpu_is_pxa27x()) {
/* Use GPIO 113 as AC97 Reset on Bulverde */
pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
}
clk_enable(ac97_clk);
return 0;
}
/*----------------------------------------------------------------------------*/
void
busFreeIrq(void)
{
#if defined(WLAN_STA_IRQ_GPIO)
pxa_gpio_mode(WLAN_STA_IRQ_GPIO | GPIO_OUT);
#endif
}
static void __init common_init(void)
{
pm_power_off = spitz_poweroff;
arm_pm_restart = spitz_restart;
PMCR = 0x00;
/* setup sleep mode values */
PWER = 0x00000002;
PFER = 0x00000000;
PRER = 0x00000002;
PGSR0 = 0x0158C000;
PGSR1 = 0x00FF0080;
PGSR2 = 0x0001C004;
/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
PCFR |= PCFR_OPDE;
corgi_ssp_set_machinfo(&spitz_ssp_machinfo);
pxa_gpio_mode(SPITZ_GPIO_HSYNC | GPIO_IN);
platform_add_devices(devices, ARRAY_SIZE(devices));
pxa_set_mci_info(&spitz_mci_platform_data);
pxa_set_ohci_info(&spitz_ohci_platform_data);
pxa_set_ficp_info(&spitz_ficp_platform_data);
set_pxa_fb_parent(&spitzssp_device.dev);
set_pxa_fb_info(&spitz_pxafb_info);
}
static void spitz_presuspend(void)
{
spitz_last_ac_status = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN);
/* GPIO Sleep Register */
PGSR0 = 0x00144018;
PGSR1 = 0x00EF0000;
if (machine_is_akita()) {
PGSR2 = 0x2121C000;
PGSR3 = 0x00600400;
} else {
PGSR2 = 0x0121C000;
PGSR3 = 0x00600000;
}
PGSR0 &= ~SPITZ_GPIO_G0_STROBE_BIT;
PGSR1 &= ~SPITZ_GPIO_G1_STROBE_BIT;
PGSR2 &= ~SPITZ_GPIO_G2_STROBE_BIT;
PGSR3 &= ~SPITZ_GPIO_G3_STROBE_BIT;
PGSR2 |= GPIO_bit(SPITZ_GPIO_KEY_STROBE0);
pxa_gpio_mode(GPIO18_RDY|GPIO_OUT | GPIO_DFLT_HIGH);
PRER = GPIO_bit(SPITZ_GPIO_KEY_INT);
PFER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET);
PWER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET) | PWER_RTC;
PKWR = GPIO_bit(SPITZ_GPIO_SYNC) | GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET);
PKSR = 0xffffffff; // clear
/* nRESET_OUT Disable */
PSLR |= PSLR_SL_ROD;
/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
PCFR = PCFR_GPR_EN | PCFR_OPDE;
}
static int roverp5p_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
{
unsigned long flags;
skt->irq = IRQ_GPIO(GPIO_NR_ROVERP5P_PXA_PRDY);
local_irq_save (flags);
pxa_gpio_mode (GPIO_NR_ROVERP5P_CF_RESET | GPIO_OUT);
pxa_gpio_mode (GPIO_NR_ROVERP5P_CF_PWR_ON | GPIO_OUT);
pxa_gpio_mode (GPIO_NR_ROVERP5P_CF_BUS_nON | GPIO_OUT);
pxa_gpio_mode (GPIO_NR_ROVERP5P_CF_DETECT | GPIO_IN);
pxa_gpio_mode (GPIO_NR_ROVERP5P_PXA_PRDY | GPIO_IN);
local_irq_restore (flags);
return soc_pcmcia_request_irqs(skt, cd_irqs, ARRAY_SIZE(cd_irqs));
}
static void pxa2xx_ac97_reset(ac97_t *ac97)
{
/* First, try cold reset */
GCR &= GCR_COLD_RST; /* clear everything but nCRST */
GCR &= ~GCR_COLD_RST; /* then assert nCRST */
gsr_bits = 0;
#ifdef CONFIG_PXA27x
/* PXA27x Developers Manual section 13.5.2.2.1 */
pxa_set_cken(1 << 31, 1);
udelay(5);
pxa_set_cken(1 << 31, 0);
GCR = GCR_COLD_RST;
udelay(50);
#else
GCR = GCR_COLD_RST;
GCR |= GCR_PRIRDY_IEN|GCR_SECRDY_IEN;
wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
#endif
if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
__FUNCTION__, gsr_bits);
/* let's try warm reset */
gsr_bits = 0;
#ifdef CONFIG_PXA27x
/* warm reset broken on Bulverde,
so manually keep AC97 reset high */
pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH);
udelay(10);
GCR |= GCR_WARM_RST;
pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
udelay(50);
#else
GCR |= GCR_WARM_RST|GCR_PRIRDY_IEN|GCR_SECRDY_IEN;;
wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
#endif
if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
__FUNCTION__, gsr_bits);
}
GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
}
