/**
* @brief Configures the FMC and GPIOs to interface with the SDRAM memory.
* This function must be called before any read/write operation
* on the SDRAM.
* @param None
* @retval None
*/
void SDRAM_Init(void)
{
FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure;
FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure;
/* Enable FMC clock */
rccEnableAHB3(RCC_AHB3ENR_FMCEN, FALSE);
/* FMC Configuration ---------------------------------------------------------*/
/* FMC SDRAM Bank configuration */
/* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */
/* TMRD: 2 Clock cycles */
FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
/* TXSR: min=70ns (6x11.90ns) */
FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7;
/* TRAS: min=42ns (4x11.90ns) max=120k (ns) */
FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
/* TRC: min=63 (6x11.90ns) */
FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7;
/* TWR: 2 Clock cycles */
FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
/* TRP: 15ns => 2x11.90ns */
FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
/* TRCD: 15ns => 2x11.90ns */
FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
/* FMC SDRAM control configuration */
FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM;
/* Row addressing: [7:0] */
FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
/* Column addressing: [11:0] */
FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b;
FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH;
FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY;
FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD;
FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST;
FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
/* FMC SDRAM bank initialization */
FMC_SDRAMInit(&FMC_SDRAMInitStructure);
/* FMC SDRAM device initialization sequence */
SDRAM_InitSequence();
}
/*
* Board-specific initialization code.
*/
void boardInit(void) {
rccEnableAHB3(RCC_AHB3ENR_FSMCEN, FALSE);
// Bank 1 Control Register
FSMC_Bank1->BTCR[0] = FSMC_BCR1_MBKEN | FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_EXTMOD;
// Bank 1 Read Timing Register
FSMC_Bank1->BTCR[1] =
FSMC_BTR1_CLKDIV_0 |
FSMC_BTR1_ADDSET_0 |
FSMC_BTR1_DATAST_0 | FSMC_BTR1_DATAST_2;
// Bank 1 Write Timing Register
FSMC_Bank1E->BWTR[0] =
FSMC_BWTR1_CLKDIV_0 |
FSMC_BWTR1_ADDSET_0 |
FSMC_BWTR1_DATAST_1;
adcStart(&ADCD1, NULL);
adcSTM32EnableTSVREFE();
}
/**
* @brief Low level GDISP driver initialisation.
* @return TRUE if successful, FALSE on error.
*
* @notapi
*/
bool_t GDISP_LLD(init)(void) {
/* Initialise the display */
#if defined(GDISP_USE_FSMC)
#if defined(STM32F1XX) || defined(STM32F3XX)
/* FSMC setup for F1/F3 */
rccEnableAHB(RCC_AHBENR_FSMCEN, 0);
#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
#error "DMA not implemented for F1/F3 Devices"
#endif
#elif defined(STM32F4XX) || defined(STM32F2XX)
/* STM32F2-F4 FSMC init */
rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
if (dmaStreamAllocate(GDISP_DMA_STREAM, 0, NULL, NULL)) chSysHalt();
dmaStreamSetMemory0(GDISP_DMA_STREAM, &GDISP_RAM);
dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
#endif
#else
#error "FSMC not implemented for this device"
#endif
/* set pins to FSMC mode */
IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
(1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0};
IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
(1 << 13) | (1 << 14) | (1 << 15), 0};
palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
const unsigned char FSMC_Bank = 0;
/* FSMC timing */
FSMC_Bank1->BTCR[FSMC_Bank+1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \
| (FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_3) \
| (FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_3) ;
/* Bank1 NOR/SRAM control register configuration
* This is actually not needed as already set by default after reset */
FSMC_Bank1->BTCR[FSMC_Bank] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
#elif defined(GDISP_USE_GPIO)
IOBus busCMD = {GDISP_CMD_PORT, (1 << GDISP_CS) | (1 << GDISP_RS) | (1 << GDISP_WR) | (1 << GDISP_RD), 0};
IOBus busDATA = {GDISP_CMD_PORT, 0xFFFFF, 0};
palSetBusMode(&busCMD, PAL_MODE_OUTPUT_PUSHPULL);
palSetBusMode(&busDATA, PAL_MODE_OUTPUT_PUSHPULL);
#else
#error "Please define GDISP_USE_FSMC or GDISP_USE_GPIO"
#endif
GDISP_LLD(writeindex)(SSD1963_SOFT_RESET);
chThdSleepMicroseconds(100);
/* Driver PLL config */
GDISP_LLD(writeindex)(SSD1963_SET_PLL_MN);
GDISP_LLD(writedata)(35); // PLLclk = REFclk (10Mhz) * 36 (360Mhz)
GDISP_LLD(writedata)(2); // SYSclk = PLLclk / 3 (120MHz)
GDISP_LLD(writedata)(4); // Apply calculation bit, else it is ignored
GDISP_LLD(writeindex)(SSD1963_SET_PLL); // Enable PLL
GDISP_LLD(writedata)(0x01);
chThdSleepMicroseconds(200);
GDISP_LLD(writeindex)(SSD1963_SET_PLL); // Use PLL
GDISP_LLD(writedata)(0x03);
chThdSleepMicroseconds(200);
GDISP_LLD(writeindex)(SSD1963_SOFT_RESET);
chThdSleepMicroseconds(100);
/* Screen size */
GDISP_LLD(writeindex)(SSD1963_SET_GDISP_MODE);
// GDISP_LLD(writedata)(0x0000);
GDISP_LLD(writedata)(0b00011000); //Enabled dithering
GDISP_LLD(writedata)(0x0000);
GDISP_LLD(writedata)(mHIGH((GDISP_SCREEN_WIDTH+1)));
GDISP_LLD(writedata)((GDISP_SCREEN_WIDTH+1));
GDISP_LLD(writedata)(mHIGH((GDISP_SCREEN_HEIGHT+1)));
GDISP_LLD(writedata)((GDISP_SCREEN_HEIGHT+1));
GDISP_LLD(writedata)(0x0000);
GDISP_LLD(writeindex)(SSD1963_SET_PIXEL_DATA_INTERFACE);
GDISP_LLD(writedata)(SSD1963_PDI_16BIT565);
/* LCD Clock specs */
GDISP_LLD(writeindex)(SSD1963_SET_LSHIFT_FREQ);
GDISP_LLD(writedata)((GDISP_FPR >> 16) & 0xFF);
GDISP_LLD(writedata)((GDISP_FPR >> 8) & 0xFF);
GDISP_LLD(writedata)(GDISP_FPR & 0xFF);
GDISP_LLD(writeindex)(SSD1963_SET_HORI_PERIOD);
GDISP_LLD(writedata)(mHIGH(SCREEN_HSYNC_PERIOD));
GDISP_LLD(writedata)(mLOW(SCREEN_HSYNC_PERIOD));
GDISP_LLD(writedata)(mHIGH((SCREEN_HSYNC_PULSE + SCREEN_HSYNC_BACK_PORCH)));
GDISP_LLD(writedata)(mLOW((SCREEN_HSYNC_PULSE + SCREEN_HSYNC_BACK_PORCH)));
GDISP_LLD(writedata)(SCREEN_HSYNC_PULSE);
GDISP_LLD(writedata)(0x00);
GDISP_LLD(writedata)(0x00);
GDISP_LLD(writedata)(0x00);
GDISP_LLD(writeindex)(SSD1963_SET_VERT_PERIOD);
GDISP_LLD(writedata)(mHIGH(SCREEN_VSYNC_PERIOD));
GDISP_LLD(writedata)(mLOW(SCREEN_VSYNC_PERIOD));
GDISP_LLD(writedata)(mHIGH((SCREEN_VSYNC_PULSE + SCREEN_VSYNC_BACK_PORCH)));
GDISP_LLD(writedata)(mLOW((SCREEN_VSYNC_PULSE + SCREEN_VSYNC_BACK_PORCH)));
GDISP_LLD(writedata)(SCREEN_VSYNC_PULSE);
GDISP_LLD(writedata)(0x00);
GDISP_LLD(writedata)(0x00);
/* Tear effect indicator ON. This is used to tell the host MCU when the driver is not refreshing the panel */
GDISP_LLD(writeindex)(SSD1963_SET_TEAR_ON);
GDISP_LLD(writedata)(0x0000);
/* Turn on */
GDISP_LLD(writeindex)(SSD1963_SET_DISPLAY_ON);
#if defined(GDISP_USE_FSMC)
/* FSMC delay reduced as the controller now runs at full speed */
FSMC_Bank1->BTCR[FSMC_Bank+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ;
FSMC_Bank1->BTCR[FSMC_Bank] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
#endif
/* Initialise the GDISP structure to match */
GDISP.Width = GDISP_SCREEN_WIDTH;
GDISP.Height = GDISP_SCREEN_HEIGHT;
GDISP.Orientation = GDISP_ROTATE_0;
GDISP.Powermode = powerOn;
GDISP.Backlight = 100;
GDISP.Contrast = 50;
#if GDISP_NEED_VALIDATION || GDISP_NEED_CLIP
GDISP.clipx0 = 0;
GDISP.clipy0 = 0;
GDISP.clipx1 = GDISP.Width;
GDISP.clipy1 = GDISP.Height;
#endif
return TRUE;
}
