void Timer_t::Init() {
#if defined STM32L1XX
if(ANY_OF_3(ITmr, TIM9, TIM10, TIM11)) PClk = &Clk.APB2FreqHz;
else PClk = &Clk.APB1FreqHz;
if (ITmr == TIM2) { rccEnableTIM2(FALSE); }
else if(ITmr == TIM3) { rccEnableTIM3(FALSE); }
else if(ITmr == TIM4) { rccEnableTIM4(FALSE); }
else if(ITmr == TIM6) { rccEnableAPB1(RCC_APB1ENR_TIM6EN, FALSE); }
else if(ITmr == TIM7) { rccEnableAPB1(RCC_APB1ENR_TIM7EN, FALSE); }
else if(ITmr == TIM9) { rccEnableAPB2(RCC_APB2ENR_TIM9EN, FALSE); }
else if(ITmr == TIM10) { rccEnableAPB2(RCC_APB2ENR_TIM10EN, FALSE); }
else if(ITmr == TIM11) { rccEnableAPB2(RCC_APB2ENR_TIM11EN, FALSE); }
#elif defined STM32F0XX
if (ITmr == TIM1) { rccEnableTIM1(FALSE); }
else if(ITmr == TIM2) { rccEnableTIM2(FALSE); }
else if(ITmr == TIM3) { rccEnableTIM3(FALSE); }
#ifdef TIM6
else if(ITmr == TIM6) { rccEnableAPB1(RCC_APB1ENR_TIM6EN, FALSE); }
#endif
else if(ITmr == TIM14) { RCC->APB1ENR |= RCC_APB1ENR_TIM14EN; }
#ifdef TIM15
else if(ITmr == TIM15) { RCC->APB2ENR |= RCC_APB2ENR_TIM15EN; }
#endif
else if(ITmr == TIM16) { RCC->APB2ENR |= RCC_APB2ENR_TIM16EN; }
else if(ITmr == TIM17) { RCC->APB2ENR |= RCC_APB2ENR_TIM17EN; }
// Clock src
PClk = &Clk.APBFreqHz;
#elif defined STM32F2XX || defined STM32F4XX
if(ANY_OF_5(ITmr, TIM1, TIM8, TIM9, TIM10, TIM11)) PClk = &Clk.APB2FreqHz;
else PClk = &Clk.APB1FreqHz;
if (ITmr == TIM1) { rccEnableTIM1(FALSE); }
else if(ITmr == TIM2) { rccEnableTIM2(FALSE); }
else if(ITmr == TIM3) { rccEnableTIM3(FALSE); }
else if(ITmr == TIM4) { rccEnableTIM4(FALSE); }
else if(ITmr == TIM5) { rccEnableTIM5(FALSE); }
else if(ITmr == TIM6) { rccEnableTIM6(FALSE); }
else if(ITmr == TIM7) { rccEnableTIM7(FALSE); }
else if(ITmr == TIM8) { rccEnableTIM8(FALSE); }
else if(ITmr == TIM9) { rccEnableTIM9(FALSE); }
else if(ITmr == TIM10) { RCC->APB2ENR |= RCC_APB2ENR_TIM10EN; }
else if(ITmr == TIM11) { rccEnableTIM11(FALSE); }
else if(ITmr == TIM12) { rccEnableTIM12(FALSE); }
else if(ITmr == TIM13) { RCC->APB1ENR |= RCC_APB1ENR_TIM13EN; }
else if(ITmr == TIM14) { rccEnableTIM14(FALSE); }
#elif defined STM32F10X_LD_VL
if(ANY_OF_4(ITmr, TIM1, TIM15, TIM16, TIM17)) PClk = &Clk.APB2FreqHz;
else PClk = &Clk.APB1FreqHz;
if (ITmr == TIM1) { rccEnableTIM1(FALSE); }
else if(ITmr == TIM2) { rccEnableTIM2(FALSE); }
else if(ITmr == TIM3) { rccEnableTIM3(FALSE); }
else if(ITmr == TIM15) { RCC->APB2ENR |= RCC_APB2ENR_TIM15EN; }
else if(ITmr == TIM16) { RCC->APB2ENR |= RCC_APB2ENR_TIM16EN; }
else if(ITmr == TIM17) { RCC->APB2ENR |= RCC_APB2ENR_TIM17EN; }
#endif
}
void Timer_t::Init() {
if(ANY_OF_3(ITmr, TIM9, TIM10, TIM11)) PClk = &Clk.APB2FreqHz;
else PClk = &Clk.APB1FreqHz;
if (ITmr == TIM2) { rccEnableTIM2(FALSE); }
else if(ITmr == TIM3) { rccEnableTIM3(FALSE); }
else if(ITmr == TIM4) { rccEnableTIM4(FALSE); }
else if(ITmr == TIM6) { rccEnableAPB1(RCC_APB1ENR_TIM6EN, FALSE); }
else if(ITmr == TIM7) { rccEnableAPB1(RCC_APB1ENR_TIM7EN, FALSE); }
else if(ITmr == TIM9) { rccEnableAPB2(RCC_APB2ENR_TIM9EN, FALSE); }
else if(ITmr == TIM10) { rccEnableAPB2(RCC_APB2ENR_TIM10EN, FALSE); }
else if(ITmr == TIM11) { rccEnableAPB2(RCC_APB2ENR_TIM11EN, FALSE); }
}
void Timer_t::Init(TIM_TypeDef* Tmr) {
ITmr = Tmr;
if (ITmr == TIM2) { rccEnableTIM2(FALSE); }
else if(ITmr == TIM3) { rccEnableTIM3(FALSE); }
else if(ITmr == TIM4) { rccEnableTIM4(FALSE); }
else if(ITmr == TIM6) { rccEnableAPB1(RCC_APB1ENR_TIM6EN, FALSE); }
else if(ITmr == TIM7) { rccEnableAPB1(RCC_APB1ENR_TIM7EN, FALSE); }
else if(ITmr == TIM9) { rccEnableAPB2(RCC_APB2ENR_TIM9EN, FALSE); }
else if(ITmr == TIM10) { rccEnableAPB2(RCC_APB2ENR_TIM10EN, FALSE); }
else if(ITmr == TIM11) { rccEnableAPB2(RCC_APB2ENR_TIM11EN, FALSE); }
// Clock src
if(ANY_OF_3(ITmr, TIM9, TIM10, TIM11)) PClk = &Clk.APB2FreqHz;
else PClk = &Clk.APB1FreqHz;
}
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
/* Reset of all peripherals.*/
rccResetAHB(~RCC_AHBRSTR_FLITFRST);
rccResetAPB1(~RCC_APB1RSTR_PWRRST);
rccResetAPB2(~0);
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
/* SysTick initialization using the system clock.*/
SysTick->LOAD = Clk.AHBFreqHz / CH_FREQUENCY - 1;
SysTick->VAL = 0;
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk |
SysTick_CTRL_TICKINT_Msk;
/* DWT cycle counter enable.*/
// SCS_DEMCR |= SCS_DEMCR_TRCENA;
// DWT_CTRL |= DWT_CTRL_CYCCNTENA;
/* PWR clock enabled.*/
rccEnablePWRInterface(FALSE);
/* Initializes the backup domain.*/
// hal_lld_backup_domain_init();
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
#endif /* STM32_PVD_ENABLE */
}
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
/* Reset of all peripherals.*/
rccResetAHB(0xFFFFFFFF);
rccResetAPB1(0xFFFFFFFF);
rccResetAPB2(0xFFFFFFFF);
/* PWR clock enabled.*/
rccEnablePWRInterface(FALSE);
/* Initializes the backup domain.*/
hal_lld_backup_domain_init();
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
#endif /* STM32_PVD_ENABLE */
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
}
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
/* Reset of all peripherals.
Note, GPIOs are not reset because initialized before this point in
board files.*/
rccResetAHB(~STM32_GPIO_EN_MASK);
rccResetAPB1(0xFFFFFFFF);
rccResetAPB2(0xFFFFFFFF);
/* PWR clock enabled.*/
rccEnablePWRInterface(true);
/* Initializes the backup domain.*/
hal_lld_backup_domain_init();
/* DMA subsystems initialization.*/
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
/* IRQ subsystem initialization.*/
irqInit();
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
#endif /* STM32_PVD_ENABLE */
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
}
void cc1101_t::Init() {
// ==== GPIO ====
PinSetupOut (GPIOA, CC_CS, omPushPull, pudNone);
PinSetupAlterFunc(GPIOA, CC_SCK, omPushPull, pudNone, AF5);
PinSetupAlterFunc(GPIOA, CC_MISO, omPushPull, pudNone, AF5);
PinSetupAlterFunc(GPIOA, CC_MOSI, omPushPull, pudNone, AF5);
PinSetupIn (GPIOA, CC_GDO0, pudNone);
PinSetupIn (GPIOA, CC_GDO2, pudNone);
CsHi();
// ==== SPI ==== MSB first, master, SCK idle low, Baudrate=f/2
rccEnableSPI1(FALSE);
// NoCRC, FullDuplex, 8bit, MSB, Baudrate, Master, ClkLowIdle(CPOL=0),
// FirstEdge(CPHA=0), NSS software controlled and is 1
CC_SPI->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR;
CC_SPI->CR2 = 0;
CC_SPI->I2SCFGR &= ~((uint16_t)SPI_I2SCFGR_I2SMOD);
CC_SPI->CR1 |= SPI_CR1_SPE; // Enable SPI
// ==== Init CC ====
CReset();
FlushRxFIFO();
RfConfig();
// ==== IRQ ====
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, FALSE); // Enable sys cfg controller
SYSCFG->EXTICR[1] &= 0xFFFFFFF0; // EXTI4 is connected to PortA
// Configure EXTI line
EXTI->IMR |= GPIO0_IRQ_MASK; // Interrupt mode enabled
EXTI->EMR &= ~GPIO0_IRQ_MASK; // Event mode disabled
EXTI->RTSR &= ~GPIO0_IRQ_MASK; // Rising trigger disabled
EXTI->FTSR |= GPIO0_IRQ_MASK; // Falling trigger enabled
EXTI->PR = GPIO0_IRQ_MASK; // Clean irq flag
nvicEnableVector(EXTI4_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
}
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
/* Reset of all peripherals.*/
rccResetAHB(0xFFFFFFFF);
rccResetAPB1(0xFFFFFFFF);
rccResetAPB2(0xFFFFFFFF);
/* PWR clock enabled.*/
rccEnablePWRInterface(FALSE);
/* Initializes the backup domain.*/
hal_lld_backup_domain_init();
/* DMA subsystems initialization.*/
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
/* IRQ subsystem initialization.*/
irqInit();
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
#endif /* STM32_PVD_ENABLE */
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
#if STM32_HAS_USB
/* USB IRQ relocated to not conflict with CAN.*/
SYSCFG->CFGR1 |= SYSCFG_CFGR1_USB_IT_RMP;
#endif
}
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
/* Reset of all peripherals.*/
rccResetAHB(~RCC_AHBRSTR_FLITFRST);
rccResetAPB1(~RCC_APB1RSTR_PWRRST);
rccResetAPB2(~0);
/* PWR clock enabled.*/
rccEnablePWRInterface(FALSE);
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
// @KL
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
#endif /* STM32_PVD_ENABLE */
}
void Infrared_t::RxInit() {
chEvtInit(&IEvtSrcIrRx);
// GPIO
PinSetupOut(IR_RX_PWR_GPIO, IR_RX_PWR_PIN, omPushPull); // }
PinSet(IR_RX_PWR_GPIO, IR_RX_PWR_PIN); // } Power
PinSetupIn(IR_RX_IN_GPIO, IR_RX_IN_PIN, pudNone); // Input
// ==== Timer ====
RxTimer.Init();
RxTimer.Enable();
RxTimer.SetTopValue(0xFFFF); // Maximum
RxTimer.SetupPrescaler(1000000); // Input Freq: 1 MHz => one tick = 1 uS
//RxTimer.Disable();
// ==== Input queue ====
chMBInit(&imailbox, IRxBuf, IR_RXBUF_SZ);
// ==== Receiving thread ====
chThdCreateStatic(waIRRxThread, sizeof(waIRRxThread), NORMALPRIO, IRRxThread, NULL);
// ==== IRQ ==== PC5
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, FALSE); // Enable sys cfg controller
SYSCFG->EXTICR[1] &= 0xFFFFFF0F; // EXTI5 is connected to PortC
SYSCFG->EXTICR[1] |= 0x00000020; // EXTI5 is connected to PortC
// Configure EXTI line
EXTI->IMR |= IR_IRQ_MASK; // Interrupt mode enabled
EXTI->EMR &= ~IR_IRQ_MASK; // Event mode disabled
RxIrqWaitFalling();
EXTI->PR = IR_IRQ_MASK; // Clean irq flag
nvicEnableVector(EXTI9_5_IRQn, CORTEX_PRIORITY_MASK(IRQ_PRIO_HIGH));
}
// ================================ Timer ======================================
void Timer_t::Init() {
if (ITmr == TIM1) { rccEnableTIM1(FALSE); }
else if(ITmr == TIM2) { rccEnableTIM2(FALSE); }
else if(ITmr == TIM3) { rccEnableTIM3(FALSE); }
else if(ITmr == TIM4) { rccEnableTIM4(FALSE); }
else if(ITmr == TIM5) { rccEnableTIM5(FALSE); }
else if(ITmr == TIM8) { rccEnableTIM8(FALSE); }
else if(ITmr == TIM9) { rccEnableAPB2(RCC_APB2ENR_TIM9EN, FALSE); }
else if(ITmr == TIM10) { rccEnableAPB2(RCC_APB2ENR_TIM10EN, FALSE); }
else if(ITmr == TIM11) { rccEnableAPB2(RCC_APB2ENR_TIM11EN, FALSE); }
else if(ITmr == TIM12) { rccEnableAPB1(RCC_APB1ENR_TIM12EN, FALSE); }
else if(ITmr == TIM13) { rccEnableAPB1(RCC_APB1ENR_TIM13EN, FALSE); }
else if(ITmr == TIM14) { rccEnableAPB1(RCC_APB1ENR_TIM14EN, FALSE); }
// Clock src
if(ANY_OF_5(ITmr, TIM1, TIM8, TIM9, TIM10, TIM11)) PClk = &Clk.APB2FreqHz;
else PClk = &Clk.APB1FreqHz;
}
void LedChnl_t::Init() const {
// ==== GPIO setup ====
if(PTimer == TIM2) PinSetupAlterFunc(PGpio, Pin, omPushPull, pudNone, AF1);
else if(PTimer == TIM3 or PTimer == TIM4) PinSetupAlterFunc(PGpio, Pin, omPushPull, pudNone, AF2);
else PinSetupAlterFunc(PGpio, Pin, omPushPull, pudNone, AF3);
// ==== Timer setup ====
if (PTimer == TIM2) { rccEnableTIM2(FALSE); }
else if(PTimer == TIM3) { rccEnableTIM3(FALSE); }
else if(PTimer == TIM4) { rccEnableTIM4(FALSE); }
else if(PTimer == TIM9) { rccEnableTIM9(FALSE); }
else if(PTimer == TIM10) { rccEnableAPB2(RCC_APB2ENR_TIM10EN, FALSE); }
else if(PTimer == TIM11) { rccEnableAPB2(RCC_APB2ENR_TIM11EN, FALSE); }
PTimer->CR1 = TIM_CR1_CEN; // Enable timer, set clk division to 0, AutoReload not buffered
PTimer->CR2 = 0;
PTimer->ARR = LED_TOP_VALUE;
// ==== Timer's channel ====
#if LED_INVERTED_PWM
#define PwmMode 0b111
#else
#define PwmMode 0b110
#endif
switch(TmrChnl) {
case 1:
PTimer->CCMR1 |= (PwmMode << 4);
PTimer->CCER |= TIM_CCER_CC1E;
break;
case 2:
PTimer->CCMR1 |= (PwmMode << 12);
PTimer->CCER |= TIM_CCER_CC2E;
break;
case 3:
PTimer->CCMR2 |= (PwmMode << 4);
PTimer->CCER |= TIM_CCER_CC3E;
break;
case 4:
PTimer->CCMR2 |= (PwmMode << 12);
PTimer->CCER |= TIM_CCER_CC4E;
break;
default: break;
}
}
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
/* Reset of all peripherals.*/
rccResetAHB(0xFFFFFFFF);
rccResetAPB1(0xFFFFFFFF);
rccResetAPB2(0xFFFFFFFF);
/* SysTick initialization using the system clock.*/
SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
SysTick->VAL = 0;
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk |
SysTick_CTRL_TICKINT_Msk;
/* DWT cycle counter enable.*/
SCS_DEMCR |= SCS_DEMCR_TRCENA;
DWT_CTRL |= DWT_CTRL_CYCCNTENA;
/* PWR clock enabled.*/
rccEnablePWRInterface(FALSE);
/* Initializes the backup domain.*/
hal_lld_backup_domain_init();
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
#endif /* STM32_PVD_ENABLE */
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
/* USB IRQ relocated to not conflict with CAN.*/
SYSCFG->CFGR1 |= SYSCFG_CFGR1_USB_IT_RMP;
}
/**
* @brief STM32 I/O ports configuration.
* @details Ports A-D(E, F, G) clocks enabled, AFIO clock enabled.
*
* @param[in] config the STM32 ports configuration
*
* @notapi
*/
void _pal_lld_init(const PALConfig *config) {
/*
* Enables the GPIO related clocks.
*/
rccEnableAPB2(APB2_EN_MASK, FALSE);
/*
* Initial GPIO setup.
*/
GPIOA->ODR = config->PAData.odr;
GPIOA->CRH = config->PAData.crh;
GPIOA->CRL = config->PAData.crl;
GPIOB->ODR = config->PBData.odr;
GPIOB->CRH = config->PBData.crh;
GPIOB->CRL = config->PBData.crl;
GPIOC->ODR = config->PCData.odr;
GPIOC->CRH = config->PCData.crh;
GPIOC->CRL = config->PCData.crl;
GPIOD->ODR = config->PDData.odr;
GPIOD->CRH = config->PDData.crh;
GPIOD->CRL = config->PDData.crl;
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
GPIOE->ODR = config->PEData.odr;
GPIOE->CRH = config->PEData.crh;
GPIOE->CRL = config->PEData.crl;
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
GPIOF->ODR = config->PFData.odr;
GPIOF->CRH = config->PFData.crh;
GPIOF->CRL = config->PFData.crl;
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
GPIOG->ODR = config->PGData.odr;
GPIOG->CRH = config->PGData.crh;
GPIOG->CRL = config->PGData.crl;
#endif
#endif
#endif
}
/**
* @brief STM32F2xx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function should be invoked just after the system reset.
*
* @special
*/
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* PWR clock enable.*/
#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR_RTCAPBEN)
RCC->APB1ENR = RCC_APB1ENR_PWREN | RCC_APB1ENR_RTCAPBEN;
#else
RCC->APB1ENR = RCC_APB1ENR_PWREN;
#endif
/* PWR initialization.*/
#if defined(STM32F4XX) || defined(__DOXYGEN__)
PWR->CR = STM32_VOS;
#else
PWR->CR = 0;
#endif
/* HSI setup, it enforces the reset situation in order to handle possible
problems with JTAG probes and re-initializations.*/
RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
while (!(RCC->CR & RCC_CR_HSIRDY))
; /* Wait until HSI is stable. */
/* HSI is selected as new source without touching the other fields in
CFGR. Clearing the register has to be postponed after HSI is the
new source.*/
RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
; /* Wait until HSI is selected. */
/* Registers finally cleared to reset values.*/
RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
RCC->CFGR = 0; /* CFGR reset value. */
#if STM32_HSE_ENABLED
/* HSE activation.*/
#if defined(STM32_HSE_BYPASS)
/* HSE Bypass.*/
RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
#else
/* No HSE Bypass.*/
RCC->CR |= RCC_CR_HSEON;
#endif
while ((RCC->CR & RCC_CR_HSERDY) == 0)
; /* Waits until HSE is stable. */
#endif
#if STM32_LSI_ENABLED
/* LSI activation.*/
RCC->CSR |= RCC_CSR_LSION;
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
; /* Waits until LSI is stable. */
#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
STM32_PLLM;
RCC->CR |= RCC_CR_PLLON;
/* Synchronization with voltage regulator stabilization.*/
#if defined(STM32F4XX)
while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
; /* Waits until power regulator is stable. */
#if STM32_OVERDRIVE_REQUIRED
/* Overdrive activation performed after activating the PLL in order to save
time as recommended in RM in "Entering Over-drive mode" paragraph.*/
PWR->CR |= PWR_CR_ODEN;
while (!(PWR->CSR & PWR_CSR_ODRDY))
;
PWR->CR |= PWR_CR_ODSWEN;
while (!(PWR->CSR & PWR_CSR_ODSWRDY))
;
#endif /* STM32_OVERDRIVE_REQUIRED */
#endif /* defined(STM32F4XX) */
/* Waiting for PLL lock.*/
while (!(RCC->CR & RCC_CR_PLLRDY))
;
#endif /* STM32_ACTIVATE_PLL */
#if STM32_ACTIVATE_PLLI2S
/* PLLI2S activation.*/
RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN | STM32_PLLI2SP |
STM32_PLLI2SQ | STM32_PLLI2SM;
RCC->CR |= RCC_CR_PLLI2SON;
/* Waiting for PLL lock.*/
while (!(RCC->CR & RCC_CR_PLLI2SRDY))
;
#endif /* STM32_ACTIVATE_PLLI2S */
#if STM32_ACTIVATE_PLLSAI
/* PLLSAI activation.*/
RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIN | STM32_PLLSAIP |
STM32_PLLSAIQ | STM32_PLLSAIM;
RCC->CR |= RCC_CR_PLLSAION;
/* Waiting for PLL lock.*/
while (!(RCC->CR & RCC_CR_PLLSAIRDY))
;
#endif /* STM32_ACTIVATE_PLLSAI */
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
STM32_I2SSRC | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE;
#if defined(STM32F446xx)
/* DCKCFGR register initialization, note, must take care of the _OFF
pseudo settings.*/
{
uint32_t dckcfgr = 0;
#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
dckcfgr |= STM32_SAI2SEL;
#endif
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
dckcfgr |= STM32_SAI1SEL;
#endif
#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
dckcfgr |= STM32_PLLSAIDIVR;
#endif
RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ;
}
RCC->DCKCFGR2 = STM32_CK48MSEL;
#elif defined(STM32F469xx) || defined(STM32F479xx)
/* DCKCFGR register initialization, note, must take care of the _OFF
pseudo settings.*/
{
uint32_t dckcfgr = 0;
#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
dckcfgr |= STM32_SAI2SEL;
#endif
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
dckcfgr |= STM32_SAI1SEL;
#endif
#if STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF
dckcfgr |= STM32_PLLSAIDIVR;
#endif
RCC->DCKCFGR = dckcfgr | STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ |
STM32_CK48MSEL;
}
#endif
/* Flash setup.*/
#if !defined(STM32_REMOVE_REVISION_A_FIX)
/* Some old revisions of F4x MCUs randomly crashes with compiler
optimizations enabled AND flash caches enabled. */
if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241))
FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS;
else
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
FLASH_ACR_DCEN | STM32_FLASHBITS;
#else
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
FLASH_ACR_DCEN | STM32_FLASHBITS;
#endif
/* Switching to the configured clock source if it is different from HSI.*/
#if (STM32_SW != STM32_SW_HSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
#endif
#endif /* STM32_NO_INIT */
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
}
/**
* @brief Clocks and internal voltage initialization.
*/
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* PWR clock enable.*/
RCC->APB1ENR = RCC_APB1ENR_PWREN;
/* Core voltage setup.*/
while ((PWR->CSR & PWR_CSR_VOSF) != 0)
; /* Waits until regulator is stable. */
PWR->CR = STM32_VOS;
while ((PWR->CSR & PWR_CSR_VOSF) != 0)
; /* Waits until regulator is stable. */
/* Initial clocks setup and wait for MSI stabilization, the MSI clock is
always enabled because it is the fallback clock when PLL the fails.
Trim fields are not altered from reset values.*/
RCC->CFGR = 0;
RCC->ICSCR = (RCC->ICSCR & ~STM32_MSIRANGE_MASK) | STM32_MSIRANGE;
RCC->CR = RCC_CR_MSION;
while ((RCC->CR & RCC_CR_MSIRDY) == 0)
; /* Waits until MSI is stable. */
#if STM32_HSI16_ENABLED
/* HSI activation.*/
RCC->CR |= RCC_CR_HSION;
while ((RCC->CR & RCC_CR_HSIRDY) == 0)
; /* Waits until HSI16 is stable. */
#if STM32_HSI16_DIVIDER_ENABLED
RCC->CR |= RCC_CR_HSIDIVEN;
while ((RCC->CR & RCC_CR_HSIDIVF) == 0)
;
#endif
#endif
#if STM32_HSE_ENABLED
#if defined(STM32_HSE_BYPASS)
/* HSE Bypass.*/
RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
#endif
/* HSE activation.*/
RCC->CR |= RCC_CR_HSEON;
while ((RCC->CR & RCC_CR_HSERDY) == 0)
; /* Waits until HSE is stable. */
#endif
#if STM32_LSI_ENABLED
/* LSI activation.*/
RCC->CSR |= RCC_CSR_LSION;
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
; /* Waits until LSI is stable. */
#endif
#if STM32_LSE_ENABLED
/* LSE activation, have to unlock the register.*/
if ((RCC->CSR & RCC_CSR_LSEON) == 0) {
PWR->CR |= PWR_CR_DBP;
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->CSR |= STM32_LSEDRV | RCC_CSR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->CSR |= STM32_LSEDRV;
#endif
RCC->CSR |= RCC_CSR_LSEON;
PWR->CR &= ~PWR_CR_DBP;
}
while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
; /* Waits until LSE is stable. */
#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->CFGR |= STM32_PLLDIV | STM32_PLLMUL | STM32_PLLSRC;
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL is stable. */
#endif
#if STM32_ACTIVATE_HSI48
/* Enabling SYSCFG clock. */
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
/* Configuring SYSCFG to enable VREFINT and HSI48 VREFINT buffer. */
SYSCFG->CFGR3 = STM32_VREFINT_EN | SYSCFG_CFGR3_ENREF_HSI48;
while (!(SYSCFG->CFGR3 & SYSCFG_CFGR3_VREFINT_RDYF))
; /* Waits until VREFINT is stable. */
/* Disabling SYSCFG clock. */
rccDisableAPB2(RCC_APB2ENR_SYSCFGEN);
/* Enabling HSI48. */
RCC->CRRCR |= RCC_CRRCR_HSI48ON;
while (!(RCC->CRRCR & RCC_CRRCR_HSI48RDY))
; /* Waits until HSI48 is stable. */
#endif
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CR |= STM32_RTCPRE;
RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL |
STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
RCC->CSR |= STM32_RTCSEL;
/* Flash setup and final clock selection.*/
#if defined(STM32_FLASHBITS)
FLASH->ACR = STM32_FLASHBITS;
#endif
/* Switching to the configured clock source if it is different from MSI. */
#if (STM32_SW != STM32_SW_MSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
#endif
/* Peripherals clock sources setup.*/
RCC->CCIPR = STM32_HSI48SEL | STM32_LPTIM1SEL | STM32_I2C1SEL |
STM32_LPUART1SEL | STM32_USART2SEL | STM32_USART1SEL;
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
#endif /* STM32_NO_INIT */
}
/**
* @brief Clocks and internal voltage initialization.
*/
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* PWR clock enable.*/
RCC->APB1ENR = RCC_APB1ENR_PWREN;
/* Core voltage setup.*/
while ((PWR->CSR & PWR_CSR_VOSF) != 0)
; /* Waits until regulator is stable. */
PWR->CR = STM32_VOS;
while ((PWR->CSR & PWR_CSR_VOSF) != 0)
; /* Waits until regulator is stable. */
/* Initial clocks setup and wait for MSI stabilization, the MSI clock is
always enabled because it is the fallback clock when PLL the fails.
Trim fields are not altered from reset values.*/
RCC->CFGR = 0;
RCC->ICSCR = (RCC->ICSCR & ~STM32_MSIRANGE_MASK) | STM32_MSIRANGE;
RCC->CR = RCC_CR_MSION;
while ((RCC->CR & RCC_CR_MSIRDY) == 0)
; /* Waits until MSI is stable. */
#if STM32_HSI_ENABLED
/* HSI activation.*/
RCC->CR |= RCC_CR_HSION;
while ((RCC->CR & RCC_CR_HSIRDY) == 0)
; /* Waits until HSI is stable. */
#endif
#if STM32_HSE_ENABLED
#if defined(STM32_HSE_BYPASS)
/* HSE Bypass.*/
RCC->CR |= RCC_CR_HSEBYP;
#endif
/* HSE activation.*/
RCC->CR |= RCC_CR_HSEON;
while ((RCC->CR & RCC_CR_HSERDY) == 0)
; /* Waits until HSE is stable. */
#endif
#if STM32_LSI_ENABLED
/* LSI activation.*/
RCC->CSR |= RCC_CSR_LSION;
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
; /* Waits until LSI is stable. */
#endif
#if STM32_LSE_ENABLED
/* LSE activation, have to unlock the register.*/
if ((RCC->CSR & RCC_CSR_LSEON) == 0) {
PWR->CR |= PWR_CR_DBP;
RCC->CSR |= RCC_CSR_LSEON;
PWR->CR &= ~PWR_CR_DBP;
}
while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
; /* Waits until LSE is stable. */
#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->CFGR |= STM32_PLLDIV | STM32_PLLMUL | STM32_PLLSRC;
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL is stable. */
#endif
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CR |= STM32_RTCPRE;
RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL |
STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
RCC->CSR |= STM32_RTCSEL;
/* Flash setup and final clock selection.*/
#if defined(STM32_FLASHBITS1)
FLASH->ACR = STM32_FLASHBITS1;
#endif
#if defined(STM32_FLASHBITS2)
FLASH->ACR = STM32_FLASHBITS2;
#endif
/* Switching to the configured clock source if it is different from MSI.*/
#if (STM32_SW != STM32_SW_MSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
#endif
#endif /* STM32_NO_INIT */
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
}
/**
* @brief STM32 clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function should be invoked just after the system reset.
*
* @special
*/
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* HSI setup, it enforces the reset situation in order to handle possible
problems with JTAG probes and re-initializations.*/
RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
while (!(RCC->CR & RCC_CR_HSIRDY))
; /* Wait until HSI is stable. */
RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
RCC->CFGR = 0; /* CFGR reset value. */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
; /* Waits until HSI is selected. */
#if STM32_HSE_ENABLED
/* HSE activation.*/
#if defined(STM32_HSE_BYPASS)
/* HSE Bypass.*/
RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
#else
/* No HSE Bypass.*/
RCC->CR |= RCC_CR_HSEON;
#endif
while (!(RCC->CR & RCC_CR_HSERDY))
; /* Waits until HSE is stable. */
#endif
#if STM32_HSE14_ENABLED
/* HSI14 activation.*/
RCC->CR2 |= RCC_CR2_HSI14ON;
while (!(RCC->CR2 & RCC_CR2_HSI14RDY))
; /* Waits until HSI14 is stable. */
#endif
#if STM32_LSI_ENABLED
/* LSI activation.*/
RCC->CSR |= RCC_CSR_LSION;
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
; /* Waits until LSI is stable. */
#endif
/* Clock settings.*/
RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC |
STM32_ADCPRE | STM32_PPRE | STM32_HPRE;
RCC->CFGR2 = STM32_PREDIV;
RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW |
STM32_USART1SW;
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL is stable. */
#endif
/* Flash setup and final clock selection. */
FLASH->ACR = STM32_FLASHBITS;
/* Switching to the configured clock source if it is different from HSI.*/
#if (STM32_SW != STM32_SW_HSI)
/* Switches clock source.*/
RCC->CFGR |= STM32_SW;
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
; /* Waits selection complete. */
#endif
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
#endif /* !STM32_NO_INIT */
}
// ================================ PWM pin ====================================
void PwmPin_t::Init(GPIO_TypeDef *GPIO, uint16_t N, uint8_t TimN, uint8_t Chnl, uint16_t TopValue, bool Inverted) {
TIM_TypeDef* Tim;
switch(TimN) {
case 1:
Tim = TIM1;
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF1);
rccEnableTIM1(FALSE);
break;
case 2:
Tim = TIM2;
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF1);
rccEnableTIM2(FALSE);
break;
case 3:
Tim = TIM3;
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF2);
rccEnableTIM3(FALSE);
break;
case 4:
Tim = TIM4;
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF2);
rccEnableTIM4(FALSE);
break;
case 5:
Tim = TIM5;
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF2);
rccEnableTIM5(FALSE);
break;
case 8:
Tim = TIM8;
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF3);
rccEnableTIM8(FALSE);
break;
case 9:
Tim = TIM9;
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF3);
rccEnableAPB2(RCC_APB2ENR_TIM9EN, FALSE);
break;
case 10:
Tim = TIM10;
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF3);
rccEnableAPB2(RCC_APB2ENR_TIM10EN, FALSE);
break;
case 11:
Tim = TIM11;
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF3);
rccEnableAPB2(RCC_APB2ENR_TIM11EN, FALSE);
break;
case 12:
Tim = TIM12;
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF9);
rccEnableAPB1(RCC_APB1ENR_TIM12EN, FALSE);
break;
case 13:
Tim = TIM13;
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF9);
rccEnableAPB1(RCC_APB1ENR_TIM13EN, FALSE);
break;
case 14:
Tim = TIM14;
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF9);
rccEnableAPB1(RCC_APB1ENR_TIM14EN, FALSE);
break;
default: return; break;
}
// Common
Tim->CR1 = TIM_CR1_CEN; // Enable timer, set clk division to 0, AutoReload not buffered
Tim->CR2 = 0;
Tim->ARR = TopValue;
Tim->BDTR = TIM_BDTR_MOE | TIM_BDTR_AOE;
// Output
uint16_t tmp = Inverted? 0b111 : 0b110; // PWM mode 1 or 2
switch(Chnl) {
case 1:
PCCR = &Tim->CCR1;
Tim->CCMR1 |= (tmp << 4);
Tim->CCER |= TIM_CCER_CC1E;
break;
case 2:
PCCR = &Tim->CCR2;
Tim->CCMR1 |= (tmp << 12);
Tim->CCER |= TIM_CCER_CC2E;
break;
case 3:
PCCR = &Tim->CCR3;
Tim->CCMR2 |= (tmp << 4);
Tim->CCER |= TIM_CCER_CC3E;
break;
case 4:
PCCR = &Tim->CCR4;
Tim->CCMR2 |= (tmp << 12);
Tim->CCER |= TIM_CCER_CC4E;
break;
default: break;
}
*PCCR = 0;
}
void Lcd_t::Init() {
// ==== Backlight: Timer15 Ch2 ====
// Setup pin
PinSetupAlterFuncOutput(LCD_GPIO, LCD_BCKLT, omPushPull, ps50MHz);
// Remap Timer15 to PB14 & PB15
AFIO->MAPR2 |= 0x00000001;
// Setup timer15
rccEnableAPB2(RCC_APB2ENR_TIM15EN, false);
TIM15->CR1 = 0x01; // Enable timer
TIM15->CR2 = 0;
TIM15->PSC = 0; // Do not divide input freq
TIM15->ARR = 100; // Autoreload register: full brightness=100
TIM15->BDTR = 0xC000; // Main output Enable
TIM15->CCMR1 = 0x6000; // PWM mode1 on Ch2 enabled
TIM15->CCER = 0x0010; // Output2 enabled, polarity not inverted
BackligthValue = 0;
// ==== GPIOs ====
// Configure LCD_XRES, LCD_XCS, LCD_SCLK & LCD_SDA as Push-Pull output
InitGpios();
// ========================= Init LCD ======================================
SCLK_Lo();
XCS_Hi();
// Reset display
XRES_Lo();
chThdSleepMilliseconds(9);
XRES_Hi();
WriteCmd(0xAF); // display ON
// Reset display again
XRES_Lo();
chThdSleepMilliseconds(7);
XRES_Hi();
chThdSleepMilliseconds(7);
// Initial commands
WriteCmd(0xAF); // display ON
WriteCmd(0xA4); // Set normal display mode
WriteCmd(0x2F); // Charge pump on
WriteCmd(0x40); // Set start row address = 0
// WriteCmd(0xC8); // mirror Y axis
// WriteCmd(0xA1); // Mirror X axis
// Set x=0, y=0
WriteCmd(0xB3); // Y axis initialization
WriteCmd(0x10); // X axis initialisation1
WriteCmd(0x08); // X axis initialisation2
Cls(); // clear LCD buffer
draw_mode = OVERWRITE;
// ====================== Switch to USART + DMA ============================
#ifdef ENABLE_DMAUSART_MODE
PinSetupAlterFuncOutput(LCD_GPIO, LCD_SCLK, omPushPull, ps50MHz);
PinSetupAlterFuncOutput(LCD_GPIO, LCD_SDA, omPushPull, ps50MHz);
// Workaround hardware bug with disabled CK3 when SPI2 is enabled
SPI2->CR2 |= SPI_CR2_SSOE;
// ==== USART init ====
rccEnableUSART3(false);
// Usart clock: enabled, idle low, first edge, enable last bit pulse
// Usart itself
LCD_USART->BRR = Clk.APB1FreqHz / 100000;
LCD_USART->CR1 = USART_CR1_TE | /* Transmitter enabled */ \
USART_CR1_M; /* 9 bit */
LCD_USART->CR2 = USART_CR2_CLKEN | \
USART_CR2_LBCL;
LCD_USART->CR3 = USART_CR3_DMAT; // Enable DMA at transmitter
LCD_USART->CR1 |= USART_CR1_UE; // Enable USART
// ==== DMA ====
rccEnableDMA1();
dmaStreamAllocate(LCD_DMA, IRQ_PRIO_MEDIUM, LcdDmaCompIrq, NULL);
dmaStreamSetPeripheral(LCD_DMA, &USART3->DR);
dmaStreamSetMemory0(LCD_DMA, (uint32_t)&IBuf[0]);
dmaStreamSetMode (LCD_DMA, LCD_DMA_MODE);
// Start transmission
XCS_Lo();
// DMA_Cmd(DMA1_Channel2, ENABLE); // Enable USARTy DMA TX Channel
#else
for(int i=0; i < 864; i++) WriteData(0x00); // Clear all screen
#endif
Backlight(0);
chThdCreateStatic(waLcdThread, sizeof(waLcdThread), NORMALPRIO, (tfunc_t)LcdThread, NULL);
}
/**
* @brief STM32F2xx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function should be invoked just after the system reset.
*
* @special
*/
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* PWR clock enable.*/
RCC->APB1ENR = RCC_APB1ENR_PWREN;
/* PWR initialization.*/
#if defined(STM32F4XX) || defined(__DOXYGEN__)
PWR->CR = STM32_VOS;
while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
; /* Waits until power regulator is stable. */
#else
PWR->CR = 0;
#endif
/* Initial clocks setup and wait for HSI stabilization, the MSI clock is
always enabled because it is the fallback clock when PLL the fails.*/
RCC->CR |= RCC_CR_HSION;
while ((RCC->CR & RCC_CR_HSIRDY) == 0)
; /* Waits until HSI is stable. */
#if STM32_HSE_ENABLED
/* HSE activation.*/
#if defined(STM32_HSE_BYPASS)
/* HSE Bypass.*/
RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
#else
/* No HSE Bypass.*/
RCC->CR |= RCC_CR_HSEON;
#endif
while ((RCC->CR & RCC_CR_HSERDY) == 0)
; /* Waits until HSE is stable. */
#endif
#if STM32_LSI_ENABLED
/* LSI activation.*/
RCC->CSR |= RCC_CSR_LSION;
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
; /* Waits until LSI is stable. */
#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
STM32_PLLM;
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL is stable. */
#endif
#if STM32_ACTIVATE_PLLI2S
/* PLLI2S activation.*/
RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN;
RCC->CR |= RCC_CR_PLLI2SON;
while (!(RCC->CR & RCC_CR_PLLI2SRDY))
; /* Waits until PLLI2S is stable. */
#endif
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* Flash setup.*/
#if defined(STM32_USE_REVISION_A_FIX)
/* Some old revisions of F4x MCUs randomly crashes with compiler
optimizations enabled AND flash caches enabled. */
if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241))
FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS;
else
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
FLASH_ACR_DCEN | STM32_FLASHBITS;
#else
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
FLASH_ACR_DCEN | STM32_FLASHBITS;
#endif
/* Switching to the configured clock source if it is different from MSI.*/
#if (STM32_SW != STM32_SW_HSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
#endif
#endif /* STM32_NO_INIT */
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
}
/**
* @brief STM32F2xx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function should be invoked just after the system reset.
*
* @special
*/
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* PWR clock enable.*/
RCC->APB1ENR = RCC_APB1ENR_PWREN;
/* PWR initialization.*/
PWR->CR = STM32_VOS;
while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
; /* Waits until power regulator is stable. */
/* Initial clocks setup and wait for HSI stabilization, the MSI clock is
always enabled because it is the fallback clock when PLL the fails.*/
RCC->CR |= RCC_CR_HSION;
while ((RCC->CR & RCC_CR_HSIRDY) == 0)
; /* Waits until HSI is stable. */
#if STM32_HSE_ENABLED
/* HSE activation.*/
RCC->CR |= RCC_CR_HSEON;
while ((RCC->CR & RCC_CR_HSERDY) == 0)
; /* Waits until HSE is stable. */
#endif
#if STM32_LSI_ENABLED
/* LSI activation.*/
RCC->CSR |= RCC_CSR_LSION;
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
; /* Waits until LSI is stable. */
#endif
#if STM32_LSE_ENABLED
/* LSE activation, have to unlock the register.*/
if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) {
PWR->CR |= PWR_CR_DBP;
RCC->BDCR |= RCC_BDCR_LSEON;
PWR->CR &= ~PWR_CR_DBP;
}
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN | STM32_PLLM;
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL is stable. */
#endif
#if STM32_ACTIVATE_PLLI2S
/* PLLI2S activation.*/
RCC->PLLI2SCFGR = STM32_PLLI2SR_VALUE | STM32_PLLI2SN_VALUE;
RCC->CR |= RCC_CR_PLLI2SON;
while (!(RCC->CR & RCC_CR_PLLI2SRDY))
; /* Waits until PLLI2S is stable. */
#endif
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* Flash setup.*/
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN |
STM32_FLASHBITS;
/* Switching to the configured clock source if it is different from MSI.*/
#if (STM32_SW != STM32_SW_HSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
#endif
#endif /* STM32_NO_INIT */
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
}
// ================================ PWM pin ====================================
void PwmPin_t::Init(GPIO_TypeDef *GPIO, uint16_t N, uint8_t TimN, uint8_t Chnl, uint16_t TopValue, bool Inverted) {
PinSetupAlterFuncOutput(GPIO, N, omPushPull);
switch(TimN) {
case 1:
Tim = TIM1;
rccEnableTIM1(FALSE);
break;
case 2:
Tim = TIM2;
rccEnableTIM2(FALSE);
break;
case 3:
Tim = TIM3;
rccEnableTIM3(FALSE);
break;
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
case 4:
Tim = TIM4;
rccEnableTIM4(FALSE);
break;
#endif
case 15:
Tim = TIM15;
rccEnableAPB2(RCC_APB2ENR_TIM15EN, FALSE);
break;
case 16:
Tim = TIM16;
rccEnableAPB2(RCC_APB2ENR_TIM16EN, FALSE);
break;
case 17:
Tim = TIM17;
rccEnableAPB2(RCC_APB2ENR_TIM17EN, FALSE);
break;
default: return; break;
}
// Clock src
if(ANY_OF_4(TimN, 1, 15, 16, 17)) PClk = &Clk.APB2FreqHz;
else PClk = &Clk.APB1FreqHz;
// Common
Tim->CR1 = TIM_CR1_CEN; // Enable timer, set clk division to 0, AutoReload not buffered
Tim->CR2 = 0;
Tim->ARR = TopValue;
Tim->BDTR = TIM_BDTR_MOE | TIM_BDTR_AOE;
// Output
uint16_t tmp = Inverted? 0b111 : 0b110; // PWM mode 1 or 2
switch(Chnl) {
case 1:
PCCR = &Tim->CCR1;
Tim->CCMR1 |= (tmp << 4);
Tim->CCER |= TIM_CCER_CC1E;
break;
case 2:
PCCR = &Tim->CCR2;
Tim->CCMR1 |= (tmp << 12);
Tim->CCER |= TIM_CCER_CC2E;
break;
case 3:
PCCR = &Tim->CCR3;
Tim->CCMR2 |= (tmp << 4);
Tim->CCER |= TIM_CCER_CC3E;
break;
case 4:
PCCR = &Tim->CCR4;
Tim->CCMR2 |= (tmp << 12);
Tim->CCER |= TIM_CCER_CC4E;
break;
default: break;
}
*PCCR = 0;
}
// ================================ PWM pin ====================================
void PwmPin_t::Init(GPIO_TypeDef *GPIO, uint16_t N, TIM_TypeDef* PTim, uint8_t Chnl, uint16_t TopValue, bool Inverted) {
Tim = PTim;
if(Tim == TIM1) {
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF1);
rccEnableTIM1(FALSE);
}
else if(Tim == TIM2) {
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF1);
rccEnableTIM2(FALSE);
}
else if(Tim == TIM3) {
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF2);
rccEnableTIM3(FALSE);
}
else if(Tim == TIM4) {
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF2);
rccEnableTIM4(FALSE);
}
else if(Tim == TIM5) {
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF2);
rccEnableTIM5(FALSE);
}
else if(Tim == TIM8) {
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF3);
rccEnableTIM8(FALSE);
}
else if(Tim == TIM9) {
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF3);
rccEnableAPB2(RCC_APB2ENR_TIM9EN, FALSE);
}
else if(Tim == TIM10) {
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF3);
rccEnableAPB2(RCC_APB2ENR_TIM10EN, FALSE);
}
else if(Tim == TIM11) {
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF3);
rccEnableAPB2(RCC_APB2ENR_TIM11EN, FALSE);
}
else if(Tim == TIM12) {
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF9);
rccEnableAPB1(RCC_APB1ENR_TIM12EN, FALSE);
}
else if(Tim == TIM13) {
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF9);
rccEnableAPB1(RCC_APB1ENR_TIM13EN, FALSE);
}
else if(Tim == TIM14) {
PinSetupAlterFunc(GPIO, N, omPushPull, pudNone, AF9);
rccEnableAPB1(RCC_APB1ENR_TIM14EN, FALSE);
}
// Clock src
if(ANY_OF_5(Tim, TIM1, TIM8, TIM9, TIM10, TIM11)) PClk = &Clk.APB2FreqHz;
else PClk = &Clk.APB1FreqHz;
// Common
Tim->CR1 = TIM_CR1_CEN; // Enable timer, set clk division to 0, AutoReload not buffered
Tim->CR2 = 0;
Tim->ARR = TopValue;
Tim->BDTR = TIM_BDTR_MOE | TIM_BDTR_AOE;
// Output
uint16_t tmp = Inverted? 0b111 : 0b110; // PWM mode 1 or 2
switch(Chnl) {
case 1:
PCCR = &Tim->CCR1;
Tim->CCMR1 |= (tmp << 4);
Tim->CCER |= TIM_CCER_CC1E;
break;
case 2:
PCCR = &Tim->CCR2;
Tim->CCMR1 |= (tmp << 12);
Tim->CCER |= TIM_CCER_CC2E;
break;
case 3:
PCCR = &Tim->CCR3;
Tim->CCMR2 |= (tmp << 4);
Tim->CCER |= TIM_CCER_CC3E;
break;
case 4:
PCCR = &Tim->CCR4;
Tim->CCMR2 |= (tmp << 12);
Tim->CCER |= TIM_CCER_CC4E;
break;
default: break;
}
*PCCR = 0;
}
/**
* @brief STM32F2xx clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function should be invoked just after the system reset.
*
* @special
*/
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* PWR clock enable.*/
RCC->APB1ENR1 = RCC_APB1ENR1_PWREN;
/* Initial clocks setup and wait for MSI stabilization, the MSI clock is
always enabled because it is the fall back clock when PLL the fails.
Trim fields are not altered from reset values.*/
RCC->CR = RCC_CR_MSION | STM32_MSIRANGE_4M;
while ((RCC->CR & RCC_CR_MSIRDY) == 0)
; /* Wait until MSI is stable. */
/* Clocking from MSI, in case MSI was not the default source.*/
RCC->CFGR = 0;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)
; /* Wait until MSI is selected. */
/* Core voltage setup.*/
PWR->CR1 = STM32_VOS;
while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
; /* stable. */
#if STM32_HSI16_ENABLED
/* HSI activation.*/
RCC->CR |= RCC_CR_HSION;
while ((RCC->CR & RCC_CR_HSIRDY) == 0)
; /* Wait until HSI is stable. */
#endif
#if STM32_HSE_ENABLED
#if defined(STM32_HSE_BYPASS)
/* HSE Bypass.*/
RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
#endif
/* HSE activation.*/
RCC->CR |= RCC_CR_HSEON;
while ((RCC->CR & RCC_CR_HSERDY) == 0)
; /* Wait until HSE is stable. */
#endif
#if STM32_LSI_ENABLED
/* LSI activation.*/
RCC->CSR |= RCC_CSR_LSION;
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
; /* Wait until LSI is stable. */
#endif
/* Backup domain access enabled and left open.*/
PWR->CR1 |= PWR_CR1_DBP;
#if STM32_LSE_ENABLED
/* LSE activation.*/
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Wait until LSE is stable. */
#endif
#if STM32_MSIPLL_ENABLED
/* MSI PLL activation.*/
RCC->CR |= RCC_CR_MSIPLLEN;
#endif
#if STM32_ACTIVATE_PLL || STM32_ACTIVATE_PLLSAI1 || STM32_ACTIVATE_PLLSAI2
/* PLLM and PLLSRC are common to all PLLs.*/
RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN |
STM32_PLLQ | STM32_PLLQEN |
STM32_PLLP | STM32_PLLPEN |
STM32_PLLN | STM32_PLLM |
STM32_PLLSRC;
#endif
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->CR |= RCC_CR_PLLON;
/* Waiting for PLL lock.*/
while ((RCC->CR & RCC_CR_PLLRDY) == 0)
;
#endif /* STM32_OVERDRIVE_REQUIRED */
#if STM32_ACTIVATE_PLLSAI1
/* PLLSAI1 activation.*/
RCC->PLLSAI1CFGR = STM32_PLLSAI1R | STM32_PLLSAI1REN |
STM32_PLLSAI1Q | STM32_PLLSAI1QEN |
STM32_PLLSAI1P | STM32_PLLSAI1PEN |
STM32_PLLSAI1N;
RCC->CR |= RCC_CR_PLLSAI1ON;
/* Waiting for PLL lock.*/
while ((RCC->CR & RCC_CR_PLLSAI1RDY) == 0)
;
#endif
#if STM32_ACTIVATE_PLLSAI2
/* PLLSAI2 activation.*/
RCC->PLLSAI2CFGR = STM32_PLLSAI2R | STM32_PLLSAI2REN |
STM32_PLLSAI2P | STM32_PLLSAI2PEN |
STM32_PLLSAI2N;
RCC->CR |= RCC_CR_PLLSAI2ON;
/* Waiting for PLL lock.*/
while ((RCC->CR & RCC_CR_PLLSAI2RDY) == 0)
;
#endif
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* CCIPR register initialization, note, must take care of the _OFF
pseudo settings.*/
{
uint32_t ccipr = STM32_DFSDMSEL | STM32_SWPMI1SEL | STM32_ADCSEL |
STM32_CLK48SEL | STM32_LPTIM2SEL | STM32_LPTIM1SEL |
STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
STM32_UART5SEL | STM32_UART4SEL | STM32_USART3SEL |
STM32_USART2SEL | STM32_USART1SEL | STM32_LPUART1SEL;
#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
ccipr |= STM32_SAI2SEL;
#endif
#if STM32_SAI1SEL != STM32_SAI1SEL_OFF
ccipr |= STM32_SAI1SEL;
#endif
RCC->CCIPR = ccipr;
}
/* Flash setup.*/
FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
STM32_FLASHBITS;
/* Switching to the configured clock source if it is different from MSI.*/
#if (STM32_SW != STM32_SW_MSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
#endif
#endif /* STM32_NO_INIT */
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
}
