void Timer_t::Init() {
#if defined STM32L1XX
if(ANY_OF_3(ITmr, TIM9, TIM10, TIM11)) PClk = &Clk.APB2FreqHz;
else PClk = &Clk.APB1FreqHz;
if (ITmr == TIM2) { rccEnableTIM2(FALSE); }
else if(ITmr == TIM3) { rccEnableTIM3(FALSE); }
else if(ITmr == TIM4) { rccEnableTIM4(FALSE); }
else if(ITmr == TIM6) { rccEnableAPB1(RCC_APB1ENR_TIM6EN, FALSE); }
else if(ITmr == TIM7) { rccEnableAPB1(RCC_APB1ENR_TIM7EN, FALSE); }
else if(ITmr == TIM9) { rccEnableAPB2(RCC_APB2ENR_TIM9EN, FALSE); }
else if(ITmr == TIM10) { rccEnableAPB2(RCC_APB2ENR_TIM10EN, FALSE); }
else if(ITmr == TIM11) { rccEnableAPB2(RCC_APB2ENR_TIM11EN, FALSE); }
#elif defined STM32F0XX
if (ITmr == TIM1) { rccEnableTIM1(FALSE); }
else if(ITmr == TIM2) { rccEnableTIM2(FALSE); }
else if(ITmr == TIM3) { rccEnableTIM3(FALSE); }
#ifdef TIM6
else if(ITmr == TIM6) { rccEnableAPB1(RCC_APB1ENR_TIM6EN, FALSE); }
#endif
else if(ITmr == TIM14) { RCC->APB1ENR |= RCC_APB1ENR_TIM14EN; }
#ifdef TIM15
else if(ITmr == TIM15) { RCC->APB2ENR |= RCC_APB2ENR_TIM15EN; }
#endif
else if(ITmr == TIM16) { RCC->APB2ENR |= RCC_APB2ENR_TIM16EN; }
else if(ITmr == TIM17) { RCC->APB2ENR |= RCC_APB2ENR_TIM17EN; }
// Clock src
PClk = &Clk.APBFreqHz;
#elif defined STM32F2XX || defined STM32F4XX
if(ANY_OF_5(ITmr, TIM1, TIM8, TIM9, TIM10, TIM11)) PClk = &Clk.APB2FreqHz;
else PClk = &Clk.APB1FreqHz;
if (ITmr == TIM1) { rccEnableTIM1(FALSE); }
else if(ITmr == TIM2) { rccEnableTIM2(FALSE); }
else if(ITmr == TIM3) { rccEnableTIM3(FALSE); }
else if(ITmr == TIM4) { rccEnableTIM4(FALSE); }
else if(ITmr == TIM5) { rccEnableTIM5(FALSE); }
else if(ITmr == TIM6) { rccEnableTIM6(FALSE); }
else if(ITmr == TIM7) { rccEnableTIM7(FALSE); }
else if(ITmr == TIM8) { rccEnableTIM8(FALSE); }
else if(ITmr == TIM9) { rccEnableTIM9(FALSE); }
else if(ITmr == TIM10) { RCC->APB2ENR |= RCC_APB2ENR_TIM10EN; }
else if(ITmr == TIM11) { rccEnableTIM11(FALSE); }
else if(ITmr == TIM12) { rccEnableTIM12(FALSE); }
else if(ITmr == TIM13) { RCC->APB1ENR |= RCC_APB1ENR_TIM13EN; }
else if(ITmr == TIM14) { rccEnableTIM14(FALSE); }
#elif defined STM32F10X_LD_VL
if(ANY_OF_4(ITmr, TIM1, TIM15, TIM16, TIM17)) PClk = &Clk.APB2FreqHz;
else PClk = &Clk.APB1FreqHz;
if (ITmr == TIM1) { rccEnableTIM1(FALSE); }
else if(ITmr == TIM2) { rccEnableTIM2(FALSE); }
else if(ITmr == TIM3) { rccEnableTIM3(FALSE); }
else if(ITmr == TIM15) { RCC->APB2ENR |= RCC_APB2ENR_TIM15EN; }
else if(ITmr == TIM16) { RCC->APB2ENR |= RCC_APB2ENR_TIM16EN; }
else if(ITmr == TIM17) { RCC->APB2ENR |= RCC_APB2ENR_TIM17EN; }
#endif
}
// ================================ Timer ======================================
void Timer_t::Init(TIM_TypeDef *Tmr) {
ITmr = Tmr;
if (ITmr == TIM1) { rccEnableTIM1(FALSE); }
else if(ITmr == TIM2) { rccEnableTIM2(FALSE); }
else if(ITmr == TIM3) { rccEnableTIM3(FALSE); }
else if(ITmr == TIM4) { rccEnableTIM4(FALSE); }
else if(ITmr == TIM5) { rccEnableTIM5(FALSE); }
else if(ITmr == TIM7) { rccEnableTIM7(FALSE); }
else if(ITmr == TIM8) { rccEnableTIM8(FALSE); }
else if(ITmr == TIM9) { rccEnableAPB2(RCC_APB2ENR_TIM9EN, FALSE); }
else if(ITmr == TIM10) { rccEnableAPB2(RCC_APB2ENR_TIM10EN, FALSE); }
else if(ITmr == TIM11) { rccEnableAPB2(RCC_APB2ENR_TIM11EN, FALSE); }
else if(ITmr == TIM12) { rccEnableAPB1(RCC_APB1ENR_TIM12EN, FALSE); }
else if(ITmr == TIM13) { rccEnableAPB1(RCC_APB1ENR_TIM13EN, FALSE); }
else if(ITmr == TIM14) { rccEnableAPB1(RCC_APB1ENR_TIM14EN, FALSE); }
// Clock src
if(ANY_OF_5(ITmr, TIM1, TIM8, TIM9, TIM10, TIM11)) PClk = &Clk.APB2FreqHz;
else PClk = &Clk.APB1FreqHz;
}
/**
* @brief Configures and activates the DAC peripheral.
*
* @param[in] dacp pointer to the @p DACDriver object
*
* @notapi
*/
void dac_lld_start(DACDriver *dacp) {
uint32_t arr, regshift, trgo, dataoffset;
bool b;
/* If in stopped state then enables the DAC and DMA clocks.*/
if (dacp->state == DAC_STOP) {
#if STM32_DAC_USE_CHN1
if (&DACD1 == dacp) {
rccEnableDAC1(FALSE);
/* DAC1 CR data is at bits 0:15 */
regshift = 0;
dataoffset = 0;
/* Timer setup */
rccEnableTIM6(FALSE);
rccResetTIM6();
trgo = STM32_DAC_CR_TSEL_TIM6;
}
#endif
#if STM32_DAC_USE_CHN2
if (&DACD2 == dacp) {
rccEnableDAC1(FALSE);
/* DAC2 CR data is at bits 16:31 */
regshift = 16;
dataoffset = &dacp->dac->DHR12R2 - &dacp->dac->DHR12R1;
/* Timer setup */
rccEnableTIM7(FALSE);
rccResetTIM7();
trgo = STM32_DAC_CR_TSEL_TIM7;
}
#endif
#if STM32_DAC_USE_CHN3
if (&DACD3 == dacp) {
rccEnableDAC2(FALSE);
/* DAC3 CR data is at bits 0:15 */
regshift = 0;
dataoffset = 0;
/* Timer setup */
rccEnableTIM18(FALSE);
rccResetTIM18();
trgo = STM32_DAC_CR_TSEL_TIM18;
}
#endif
#if STM32_DAC_USE_CHN1 || STM32_DAC_USE_CHN2 || STM32_DAC_USE_CHN3
dacp->clock = STM32_TIMCLK1;
arr = (dacp->clock / dacp->config->frequency);
osalDbgAssert((arr <= 0xFFFF),
"invalid frequency");
/* Timer configuration.*/
dacp->tim->CR1 = 0; /* Initially stopped. */
dacp->tim->PSC = 0; /* Prescaler value. */
dacp->tim->DIER = 0;
dacp->tim->ARR = arr;
dacp->tim->EGR = TIM_EGR_UG; /* Update event. */
dacp->tim->CR2 &= (uint16_t)~TIM_CR2_MMS;
dacp->tim->CR2 |= (uint16_t)TIM_CR2_MMS_1; /* Enable TRGO updates. */
dacp->tim->CNT = 0; /* Reset counter. */
dacp->tim->SR = 0; /* Clear pending IRQs. */
/* Update Event IRQ enabled. */
/* Timer start.*/
dacp->tim->CR1 = TIM_CR1_CEN;
/* DAC configuration */
dacp->dac->CR |= ( (dacp->dac->CR & ~STM32_DAC_CR_MASK) | \
(STM32_DAC_CR_EN | STM32_DAC_CR_DMAEN | dacp->config->cr_flags) ) << regshift;
/* DMA setup. */
b = dmaStreamAllocate(dacp->dma,
dacp->irqprio,
(stm32_dmaisr_t)dac_lld_serve_tx_interrupt,
(void *)dacp);
osalDbgAssert(!b, "stream already allocated");
switch (dacp->config->dhrm) {
/* Sets the DAC data register */
case DAC_DHRM_12BIT_RIGHT:
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12R1 + dataoffset);
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
break;
case DAC_DHRM_12BIT_LEFT:
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12L1 + dataoffset);
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
break;
case DAC_DHRM_8BIT_RIGHT:
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8R1 + dataoffset);
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
break;
#if defined(STM32_HAS_DAC_CHN2) && STM32_HAS_DAC_CHN2
case DAC_DHRM_12BIT_RIGHT_DUAL:
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12RD);
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
break;
case DAC_DHRM_12BIT_LEFT_DUAL:
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR12LD);
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
break;
case DAC_DHRM_8BIT_RIGHT_DUAL:
dmaStreamSetPeripheral(dacp->dma, &dacp->dac->DHR8RD);
dacp->dmamode = (dacp->dmamode & ~STM32_DMA_CR_SIZE_MASK) |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
break;
#endif
}
dacp->dac->CR |= trgo << regshift; /* Enable timer trigger */
#endif
}
}
/**
* @brief Configures and activates the GPT peripheral.
*
* @param[in] gptp pointer to the @p GPTDriver object
*
* @notapi
*/
void gpt_lld_start(GPTDriver *gptp) {
uint16_t psc;
if (gptp->state == GPT_STOP) {
/* Clock activation.*/
#if STM32_GPT_USE_TIM1
if (&GPTD1 == gptp) {
rccEnableTIM1(FALSE);
rccResetTIM1();
#if !defined(STM32_TIM1_SUPPRESS_ISR)
nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_GPT_TIM1_IRQ_PRIORITY);
#endif
#if defined(STM32_TIM1CLK)
gptp->clock = STM32_TIM1CLK;
#else
gptp->clock = STM32_TIMCLK2;
#endif
}
#endif
#if STM32_GPT_USE_TIM2
if (&GPTD2 == gptp) {
rccEnableTIM2(FALSE);
rccResetTIM2();
#if !defined(STM32_TIM2_SUPPRESS_ISR)
nvicEnableVector(STM32_TIM2_NUMBER, STM32_GPT_TIM2_IRQ_PRIORITY);
#endif
#if defined(STM32_TIM2CLK)
gptp->clock = STM32_TIM2CLK;
#else
gptp->clock = STM32_TIMCLK1;
#endif
}
#endif
#if STM32_GPT_USE_TIM3
if (&GPTD3 == gptp) {
rccEnableTIM3(FALSE);
rccResetTIM3();
#if !defined(STM32_TIM3_SUPPRESS_ISR)
nvicEnableVector(STM32_TIM3_NUMBER, STM32_GPT_TIM3_IRQ_PRIORITY);
#endif
#if defined(STM32_TIM3CLK)
gptp->clock = STM32_TIM3CLK;
#else
gptp->clock = STM32_TIMCLK1;
#endif
}
#endif
#if STM32_GPT_USE_TIM4
if (&GPTD4 == gptp) {
rccEnableTIM4(FALSE);
rccResetTIM4();
#if !defined(STM32_TIM4_SUPPRESS_ISR)
nvicEnableVector(STM32_TIM4_NUMBER, STM32_GPT_TIM4_IRQ_PRIORITY);
#endif
#if defined(STM32_TIM4CLK)
gptp->clock = STM32_TIM4CLK;
#else
gptp->clock = STM32_TIMCLK1;
#endif
}
#endif
#if STM32_GPT_USE_TIM5
if (&GPTD5 == gptp) {
rccEnableTIM5(FALSE);
rccResetTIM5();
#if !defined(STM32_TIM5_SUPPRESS_ISR)
nvicEnableVector(STM32_TIM5_NUMBER, STM32_GPT_TIM5_IRQ_PRIORITY);
#endif
#if defined(STM32_TIM5CLK)
gptp->clock = STM32_TIM5CLK;
#else
gptp->clock = STM32_TIMCLK1;
#endif
}
#endif
#if STM32_GPT_USE_TIM6
if (&GPTD6 == gptp) {
rccEnableTIM6(FALSE);
rccResetTIM6();
#if !defined(STM32_TIM6_SUPPRESS_ISR)
nvicEnableVector(STM32_TIM6_NUMBER, STM32_GPT_TIM6_IRQ_PRIORITY);
#endif
#if defined(STM32_TIM6CLK)
gptp->clock = STM32_TIM6CLK;
#else
gptp->clock = STM32_TIMCLK1;
#endif
}
#endif
#if STM32_GPT_USE_TIM7
if (&GPTD7 == gptp) {
rccEnableTIM7(FALSE);
rccResetTIM7();
#if !defined(STM32_TIM7_SUPPRESS_ISR)
nvicEnableVector(STM32_TIM7_NUMBER, STM32_GPT_TIM7_IRQ_PRIORITY);
#endif
#if defined(STM32_TIM7CLK)
gptp->clock = STM32_TIM7CLK;
#else
gptp->clock = STM32_TIMCLK1;
#endif
}
#endif
#if STM32_GPT_USE_TIM8
if (&GPTD8 == gptp) {
rccEnableTIM8(FALSE);
rccResetTIM8();
#if !defined(STM32_TIM8_SUPPRESS_ISR)
nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_GPT_TIM8_IRQ_PRIORITY);
#endif
#if defined(STM32_TIM8CLK)
gptp->clock = STM32_TIM8CLK;
#else
gptp->clock = STM32_TIMCLK2;
#endif
}
#endif
#if STM32_GPT_USE_TIM9
if (&GPTD9 == gptp) {
rccEnableTIM9(FALSE);
rccResetTIM9();
#if !defined(STM32_TIM9_SUPPRESS_ISR)
nvicEnableVector(STM32_TIM9_NUMBER, STM32_GPT_TIM9_IRQ_PRIORITY);
#endif
#if defined(STM32_TIM9CLK)
gptp->clock = STM32_TIM9CLK;
#else
gptp->clock = STM32_TIMCLK2;
#endif
}
#endif
#if STM32_GPT_USE_TIM11
if (&GPTD11 == gptp) {
rccEnableTIM11(FALSE);
rccResetTIM11();
#if !defined(STM32_TIM11_SUPPRESS_ISR)
nvicEnableVector(STM32_TIM11_NUMBER, STM32_GPT_TIM11_IRQ_PRIORITY);
#endif
#if defined(STM32_TIM11CLK)
gptp->clock = STM32_TIM11CLK;
#else
gptp->clock = STM32_TIMCLK2;
#endif
}
#endif
#if STM32_GPT_USE_TIM12
if (&GPTD12 == gptp) {
rccEnableTIM12(FALSE);
rccResetTIM12();
#if !defined(STM32_TIM12_SUPPRESS_ISR)
nvicEnableVector(STM32_TIM12_NUMBER, STM32_GPT_TIM12_IRQ_PRIORITY);
#endif
#if defined(STM32_TIM12CLK)
gptp->clock = STM32_TIM12CLK;
#else
gptp->clock = STM32_TIMCLK1;
#endif
}
#endif
#if STM32_GPT_USE_TIM14
if (&GPTD14 == gptp) {
rccEnableTIM14(FALSE);
rccResetTIM14();
#if !defined(STM32_TIM14_SUPPRESS_ISR)
nvicEnableVector(STM32_TIM14_NUMBER, STM32_GPT_TIM14_IRQ_PRIORITY);
#endif
#if defined(STM32_TIM14CLK)
gptp->clock = STM32_TIM14CLK;
#else
gptp->clock = STM32_TIMCLK1;
#endif
}
#endif
}
/* Prescaler value calculation.*/
psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1);
osalDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,
"invalid frequency");
/* Timer configuration.*/
gptp->tim->CR1 = 0; /* Initially stopped. */
gptp->tim->CR2 = gptp->config->cr2;
gptp->tim->PSC = psc; /* Prescaler value. */
gptp->tim->SR = 0; /* Clear pending IRQs. */
gptp->tim->DIER = gptp->config->dier & /* DMA-related DIER bits. */
~STM32_TIM_DIER_IRQ_MASK;
}
/**
* @brief Configures and activates the GPT peripheral.
*
* @param[in] gptp pointer to the @p GPTDriver object
*
* @notapi
*/
void gpt_lld_start(GPTDriver *gptp) {
uint16_t psc;
if (gptp->state == GPT_STOP) {
/* Clock activation.*/
#if STM32_GPT_USE_TIM1
if (&GPTD1 == gptp) {
rccEnableTIM1(FALSE);
rccResetTIM1();
nvicEnableVector(STM32_TIM1_UP_NUMBER,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM1_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK2;
}
#endif
#if STM32_GPT_USE_TIM2
if (&GPTD2 == gptp) {
rccEnableTIM2(FALSE);
rccResetTIM2();
nvicEnableVector(STM32_TIM2_NUMBER,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM2_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1;
}
#endif
#if STM32_GPT_USE_TIM3
if (&GPTD3 == gptp) {
rccEnableTIM3(FALSE);
rccResetTIM3();
nvicEnableVector(STM32_TIM3_NUMBER,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM3_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1;
}
#endif
#if STM32_GPT_USE_TIM4
if (&GPTD4 == gptp) {
rccEnableTIM4(FALSE);
rccResetTIM4();
nvicEnableVector(STM32_TIM4_NUMBER,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM4_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1;
}
#endif
#if STM32_GPT_USE_TIM5
if (&GPTD5 == gptp) {
rccEnableTIM5(FALSE);
rccResetTIM5();
nvicEnableVector(STM32_TIM5_NUMBER,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM5_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1;
}
#endif
#if STM32_GPT_USE_TIM6
if (&GPTD6 == gptp) {
rccEnableTIM6(FALSE);
rccResetTIM6();
nvicEnableVector(STM32_TIM6_NUMBER,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM6_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1;
}
#endif
#if STM32_GPT_USE_TIM7
if (&GPTD7 == gptp) {
rccEnableTIM7(FALSE);
rccResetTIM7();
nvicEnableVector(STM32_TIM7_NUMBER,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM7_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1;
}
#endif
#if STM32_GPT_USE_TIM8
if (&GPTD8 == gptp) {
rccEnableTIM8(FALSE);
rccResetTIM8();
nvicEnableVector(STM32_TIM8_UP_NUMBER,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM8_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK2;
}
#endif
#if STM32_GPT_USE_TIM9
if (&GPTD9 == gptp) {
rccEnableTIM9(FALSE);
rccResetTIM9();
nvicEnableVector(STM32_TIM9_NUMBER,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM9_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK2;
}
#endif
#if STM32_GPT_USE_TIM11
if (&GPTD11 == gptp) {
rccEnableTIM11(FALSE);
rccResetTIM11();
nvicEnableVector(STM32_TIM11_NUMBER,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM11_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK2;
}
#endif
#if STM32_GPT_USE_TIM12
if (&GPTD12 == gptp) {
rccEnableTIM12(FALSE);
rccResetTIM12();
nvicEnableVector(STM32_TIM12_NUMBER,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM12_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1;
}
#endif
#if STM32_GPT_USE_TIM14
if (&GPTD14 == gptp) {
rccEnableTIM14(FALSE);
rccResetTIM14();
nvicEnableVector(STM32_TIM14_NUMBER,
CORTEX_PRIORITY_MASK(STM32_GPT_TIM14_IRQ_PRIORITY));
gptp->clock = STM32_TIMCLK1;
}
#endif
}
/* Prescaler value calculation.*/
psc = (uint16_t)((gptp->clock / gptp->config->frequency) - 1);
chDbgAssert(((uint32_t)(psc + 1) * gptp->config->frequency) == gptp->clock,
"gpt_lld_start(), #1", "invalid frequency");
/* Timer configuration.*/
gptp->tim->CR1 = 0; /* Initially stopped. */
gptp->tim->CR2 = TIM_CR2_CCDS; /* DMA on UE (if any). */
gptp->tim->PSC = psc; /* Prescaler value. */
gptp->tim->DIER = 0;
}
