static void ssp1_dump_registers(struct intel_mid_i2s_hdl *drv_data)
{
u32 irq_status;
void __iomem *reg = drv_data->ioaddr;
struct device *ddbg = &(drv_data->pdev->dev);
u32 status;
irq_status = read_SSSR(reg);
dev_dbg(ddbg, "dump SSSR=0x%08X\n", irq_status);
status = read_SSCR0(reg);
dev_dbg(ddbg, "dump SSCR0=0x%08X\n", status);
status = read_SSCR1(reg);
dev_dbg(ddbg, "dump SSCR1=0x%08X\n", status);
status = read_SSPSP(reg);
dev_dbg(ddbg, "dump SSPSP=0x%08X\n", status);
status = read_SSTSA(reg);
dev_dbg(ddbg, "dump SSTSA=0x%08X\n", status);
status = read_SSRSA(reg);
dev_dbg(ddbg, "dump SSRSA=0x%08X\n", status);
status = read_SSTO(reg);
dev_dbg(ddbg, "dump SSTO=0x%08X\n", status);
status = read_SSITR(reg);
dev_dbg(ddbg, "dump SSITR=0x%08X\n", status);
status = read_SSTSS(reg);
dev_dbg(ddbg, "dump SSTSS=0x%08X\n", status);
status = read_SSACD(reg);
dev_dbg(ddbg, "dump SSACD=0x%08X\n", status);
}
static void pxa2xx_spi_dma_error_stop(struct driver_data *drv_data,
const char *msg)
{
void __iomem *reg = drv_data->ioaddr;
/* Stop and reset */
DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
write_SSSR_CS(drv_data, drv_data->clear_sr);
write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
if (!pxa25x_ssp_comp(drv_data))
write_SSTO(0, reg);
pxa2xx_spi_flush(drv_data);
write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
pxa2xx_spi_unmap_dma_buffers(drv_data);
dev_err(&drv_data->pdev->dev, "%s\n", msg);
drv_data->cur_msg->state = ERROR_STATE;
tasklet_schedule(&drv_data->pump_transfers);
}
