static void __print_stack_unwind(struct abort_info *ai)
{
struct unwind_state state;
memset(&state, 0, sizeof(state));
state.registers[0] = ai->regs->r0;
state.registers[1] = ai->regs->r1;
state.registers[2] = ai->regs->r2;
state.registers[3] = ai->regs->r3;
state.registers[4] = ai->regs->r4;
state.registers[5] = ai->regs->r5;
state.registers[6] = ai->regs->r6;
state.registers[7] = ai->regs->r7;
state.registers[8] = ai->regs->r8;
state.registers[9] = ai->regs->r9;
state.registers[10] = ai->regs->r10;
state.registers[11] = ai->regs->r11;
state.registers[13] = read_mode_sp(ai->regs->spsr & CPSR_MODE_MASK);
state.registers[14] = read_mode_lr(ai->regs->spsr & CPSR_MODE_MASK);
state.registers[15] = ai->pc;
do {
EMSG_RAW(" pc 0x%08x", state.registers[15]);
} while (unwind_stack(&state));
}
/*
* Kernel or user mode unwind (32-bit execution state).
*/
static void __print_stack_unwind_arm32(struct abort_info *ai)
{
struct unwind_state_arm32 state;
vaddr_t exidx;
size_t exidx_sz;
uint32_t mode = ai->regs->spsr & CPSR_MODE_MASK;
uint32_t sp;
uint32_t lr;
vaddr_t stack;
size_t stack_size;
bool kernel_stack;
if (abort_is_user_exception(ai)) {
get_current_ta_exidx_stack(&exidx, &exidx_sz, &stack,
&stack_size);
if (!exidx) {
EMSG_RAW("Call stack not available");
return;
}
kernel_stack = false;
} else {
exidx = (vaddr_t)__exidx_start;
exidx_sz = (vaddr_t)__exidx_end - (vaddr_t)__exidx_start;
/* Kernel stack */
stack = thread_stack_start();
stack_size = thread_stack_size();
kernel_stack = true;
}
if (mode == CPSR_MODE_USR || mode == CPSR_MODE_SYS) {
sp = ai->regs->usr_sp;
lr = ai->regs->usr_lr;
} else {
sp = read_mode_sp(mode);
lr = read_mode_lr(mode);
}
memset(&state, 0, sizeof(state));
state.registers[0] = ai->regs->r0;
state.registers[1] = ai->regs->r1;
state.registers[2] = ai->regs->r2;
state.registers[3] = ai->regs->r3;
state.registers[4] = ai->regs->r4;
state.registers[5] = ai->regs->r5;
state.registers[6] = ai->regs->r6;
state.registers[7] = ai->regs->r7;
state.registers[8] = ai->regs->r8;
state.registers[9] = ai->regs->r9;
state.registers[10] = ai->regs->r10;
state.registers[11] = ai->regs->r11;
state.registers[13] = sp;
state.registers[14] = lr;
state.registers[15] = ai->pc;
print_stack_arm32(TRACE_ERROR, &state, exidx, exidx_sz, kernel_stack,
stack, stack_size);
}
uint32_t tee_svc_sys_return_helper(uint32_t ret, bool panic,
uint32_t panic_code, struct thread_svc_regs *regs)
{
if (panic) {
TAMSG("TA panicked with code 0x%x usr_sp 0x%x usr_lr 0x%x",
panic_code, read_mode_sp(CPSR_MODE_SYS),
read_mode_lr(CPSR_MODE_SYS));
}
regs->r1 = panic;
regs->r2 = panic_code;
regs->lr = (uintptr_t)thread_unwind_user_mode;
regs->spsr = read_cpsr();
return ret;
}
ctx, abort_type_to_str(ai->abort_type), ai->va,
fault_to_str(ai->abort_type, ai->fault_descr));
#ifdef ARM32
EMSG_RAW(" fsr 0x%08x ttbr0 0x%08x ttbr1 0x%08x cidr 0x%X\n",
ai->fault_descr, read_ttbr0(), read_ttbr1(),
read_contextidr());
EMSG_RAW(" cpu #%zu cpsr 0x%08x\n",
get_core_pos(), ai->regs->spsr);
EMSG_RAW(" r0 0x%08x r4 0x%08x r8 0x%08x r12 0x%08x\n",
ai->regs->r0, ai->regs->r4, ai->regs->r8, ai->regs->ip);
EMSG_RAW(" r1 0x%08x r5 0x%08x r9 0x%08x sp 0x%08x\n",
ai->regs->r1, ai->regs->r5, ai->regs->r9,
read_mode_sp(ai->regs->spsr & CPSR_MODE_MASK));
EMSG_RAW(" r2 0x%08x r6 0x%08x r10 0x%08x lr 0x%08x\n",
ai->regs->r2, ai->regs->r6, ai->regs->r10,
read_mode_lr(ai->regs->spsr & CPSR_MODE_MASK));
EMSG_RAW(" r3 0x%08x r7 0x%08x r11 0x%08x pc 0x%08x\n",
ai->regs->r3, ai->regs->r7, ai->regs->r11, ai->pc);
#endif /*ARM32*/
#ifdef ARM64
EMSG_RAW(" esr 0x%08x ttbr0 0x%08" PRIx64 " ttbr1 0x%08" PRIx64 " cidr 0x%X\n",
ai->fault_descr, read_ttbr0_el1(), read_ttbr1_el1(),
read_contextidr_el1());
EMSG_RAW(" cpu #%zu cpsr 0x%08x\n",
get_core_pos(), (uint32_t)ai->regs->spsr);
EMSG_RAW("x0 %016" PRIx64 " x1 %016" PRIx64,
ai->regs->x0, ai->regs->x1);
EMSG_RAW("x2 %016" PRIx64 " x3 %016" PRIx64,
ai->regs->x2, ai->regs->x3);
EMSG_RAW("x4 %016" PRIx64 " x5 %016" PRIx64,
ai->regs->x4, ai->regs->x5);
