/*
Perform general optimizaitions.
Basis step to do:
1. Build control flow.
2. Compute data flow dependence.
3. Compute live expression info.
Optimizations to be performed:
1. GCSE
2. DCE
3. RVI(register variable recog)
4. IVR(induction variable elimination)
5. CP(constant propagation)
6. CP(copy propagation)
7. SCCP (Sparse Conditional Constant Propagation).
8. PRE (Partial Redundancy Elimination) with strength reduction.
9. Dominator-based optimizations such as copy propagation,
constant propagation and redundancy elimination using
value numbering.
10. Must-alias analysis, to convert pointer de-references
into regular variable references whenever possible.
11. Scalar Replacement of Aggregates, to convert structure
references into scalar references that can be optimized
using the standard scalar passes.
*/
bool Region::MiddleProcess(OptCtx & oc)
{
if (g_opt_level != NO_OPT) {
PassMgr * passmgr = get_pass_mgr();
ASSERT0(passmgr);
//Perform scalar optimizations.
passmgr->performScalarOpt(oc);
}
ASSERT0(verifyRPO(oc));
BBList * bbl = get_bb_list();
if (bbl->get_elem_count() == 0) { return true; }
SimpCtx simp;
simp.set_simp_cf();
simp.set_simp_array();
simp.set_simp_select();
simp.set_simp_land_lor();
simp.set_simp_lnot();
simp.set_simp_ild_ist();
simp.set_simp_to_lowest_height();
simplifyBBlist(bbl, &simp);
if (g_cst_bb_list && SIMP_need_recon_bblist(&simp)) {
if (reconstructBBlist(oc) && g_do_cfg) {
//Before CFG building.
get_cfg()->removeEmptyBB(oc);
get_cfg()->rebuild(oc);
//After CFG building, it is perform different
//operation to before building.
get_cfg()->removeEmptyBB(oc);
get_cfg()->computeExitList();
if (g_do_cdg) {
ASSERT0(get_pass_mgr());
CDG * cdg = (CDG*)get_pass_mgr()->registerPass(PASS_CDG);
cdg->rebuild(oc, *get_cfg());
}
}
}
ASSERT0(verifyIRandBB(bbl, this));
if (g_do_refine) {
RefineCtx rf;
refineBBlist(bbl, rf);
ASSERT0(verifyIRandBB(bbl, this));
}
return true;
}
//This function outputs Prno2Vreg after Dex register allocation.
bool DexRegion::process(OptCtx * oc)
{
if (getIRList() == NULL) { return true; }
OC_show_comp_time(*oc) = g_show_comp_time;
g_indent = 0;
if (!g_silence) {
LOG("DexRegion process %s", getRegionName());
}
//note("\n==---- REGION_NAME:%s ----==", getRegionName());
prescan(getIRList());
PassMgr * passmgr = initPassMgr();
HighProcess(*oc);
MiddleProcess(*oc);
ASSERT0(getPassMgr());
PRSSAMgr * ssamgr = (PRSSAMgr*)passmgr->queryPass(PASS_PR_SSA_MGR);
if (ssamgr != NULL && ssamgr->isSSAConstructed()) {
ssamgr->destruction();
}
if (!g_retain_pass_mgr_for_region) {
//Destroy PassMgr.
destroyPassMgr();
}
if (!is_function()) { return true; }
///////////////////////////////////////
//DO NOT REQUEST PASS AFTER THIS LINE//
///////////////////////////////////////
BBList * bbl = getBBList();
if (bbl->get_elem_count() == 0) { return true; }
ASSERT0(verifyIRandBB(bbl, this));
RefineCtx rf;
RC_insert_cvt(rf) = false; //Do not insert cvt for DEX code.
refineBBlist(bbl, rf);
ASSERT0(verifyIRandBB(bbl, this));
if (g_do_dex_ra) {
Prno2Vreg * original_prno2vreg = getDex2IR()->getPR2Vreg();
RA ra(this,
getTypeIndexRep(),
getParamNum(),
getOrgVregNum(),
getDex2IR()->getVreg2PR(),
original_prno2vreg,
&m_var2pr);
LOG("\t\tdo DEX Register Allcation for '%s'", getRegionName());
ra.perform(*oc);
updateRAresult(ra, *getPrno2Vreg());
} else {
//Do not allocate register.
getPrno2Vreg()->clean();
getPrno2Vreg()->copy(*getDex2IR()->getPR2Vreg());
}
return true;
}
