//simulate each memory operation
void parse_buffer(cache *sim_cache, char *buffer, int s, int E, int b, int *hit, int *miss, int *evict){
int address;
char opt;
sscanf(buffer, " %s %x", &opt, &address);
int seti = get_set_value(address, s, b);
int tagi = get_tag_value(address, s, b);
//simulate cache hit
for(int i = 0; i < E; ++ i){
if((sim_cache->sets[seti].lines[i].valid == 1)
&& (sim_cache->sets[seti].lines[i].tag == tagi)){
++ (*hit);
if(opt == 'M')
++ (*hit);
refresh_last_access(sim_cache->sets[seti].lines, E, i);
return ;
}
}
//simulate cache miss while there is no need to evict
++ (*miss);
for(int i = 0; i < E; ++ i){
if(sim_cache->sets[seti].lines[i].valid == 0){
sim_cache->sets[seti].lines[i].valid = 1;
sim_cache->sets[seti].lines[i].tag = tagi;
if(opt == 'M')
++ (*hit);
refresh_last_access(sim_cache->sets[seti].lines, E, i);
return ;
}
}
//simulate cache miss and there is need to evict
++ (*evict);
for(int i = 0; i < E; ++ i){
if(sim_cache->sets[seti].lines[i].last_access == 1){
sim_cache->sets[seti].lines[i].tag = tagi;
if(opt == 'M')
++ (*hit);
refresh_last_access(sim_cache->sets[seti].lines, E, i);
return;
}
}
}
void
set_last_access_receive(ReceivePort rp)
{
if(++sequence_number == 0)
{
rp->last_access = LARGE_UINT;
refresh_last_access();
}
rp->last_access = sequence_number;
return;
}
void
set_last_access_send(SendPort sp)
{
if(++sequence_number == 0)
{
sp->last_access = LARGE_UINT;
refresh_last_access();
}
sp->last_access = sequence_number;
return;
}
