CORE_ADDR
ppc_darwin_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
struct ppc_stack_abi abi;
CORE_ADDR ret;
abi.first_greg = 3;
abi.last_greg = 10;
abi.first_freg = 1;
abi.last_freg = 13;
abi.first_vreg = 2;
abi.last_vreg = 13;
abi.fregs_shadow_gregs = 1;
abi.regs_shadow_stack = 1;
abi.structs_with_args = 1;
abi.min_argsize = 32;
abi.backchain_size = 24;
ret = ppc_push_arguments (&abi, nargs, args, sp, struct_return, struct_addr);
/* Point the inferior function call's return address at the dummy's
breakpoint. */
regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
target_store_registers (-1);
return ret;
}
static CORE_ADDR
lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int first_arg_reg = SIM_LM32_R1_REGNUM;
int num_arg_regs = 8;
int i;
/* Set the return address. */
regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);
/* If we're returning a large struct, a pointer to the address to
store it at is passed as a first hidden parameter. */
if (struct_return)
{
regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr);
first_arg_reg++;
num_arg_regs--;
sp -= 4;
}
/* Setup parameters. */
for (i = 0; i < nargs; i++)
{
struct value *arg = args[i];
struct type *arg_type = check_typedef (value_type (arg));
gdb_byte *contents;
int len;
int j;
int reg;
ULONGEST val;
/* Promote small integer types to int. */
switch (TYPE_CODE (arg_type))
{
case TYPE_CODE_INT:
case TYPE_CODE_BOOL:
case TYPE_CODE_CHAR:
case TYPE_CODE_RANGE:
case TYPE_CODE_ENUM:
if (TYPE_LENGTH (arg_type) < 4)
{
arg_type = builtin_type (gdbarch)->builtin_int32;
arg = value_cast (arg_type, arg);
}
break;
}
/* FIXME: Handle structures. */
contents = (gdb_byte *) value_contents (arg);
len = TYPE_LENGTH (arg_type);
val = extract_unsigned_integer (contents, len, byte_order);
/* First num_arg_regs parameters are passed by registers,
and the rest are passed on the stack. */
if (i < num_arg_regs)
regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);
else
{
write_memory (sp, (void *) &val, len);
sp -= 4;
}
}
/* Update stack pointer. */
regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);
/* Return adjusted stack pointer. */
return sp;
}
CORE_ADDR
ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
CORE_ADDR func_addr = find_function_addr (function, NULL);
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
/* By this stage in the proceedings, SP has been decremented by "red
zone size" + "struct return size". Fetch the stack-pointer from
before this and use that as the BACK_CHAIN. */
const CORE_ADDR back_chain = read_sp ();
/* See for-loop comment below. */
int write_pass;
/* Size of the Altivec's vector parameter region, the final value is
computed in the for-loop below. */
LONGEST vparam_size = 0;
/* Size of the general parameter region, the final value is computed
in the for-loop below. */
LONGEST gparam_size = 0;
/* Kevin writes ... I don't mind seeing tdep->wordsize used in the
calls to align_up(), align_down(), etc. because this makes it
easier to reuse this code (in a copy/paste sense) in the future,
but it is a 64-bit ABI and asserting that the wordsize is 8 bytes
at some point makes it easier to verify that this function is
correct without having to do a non-local analysis to figure out
the possible values of tdep->wordsize. */
gdb_assert (tdep->wordsize == 8);
/* Go through the argument list twice.
Pass 1: Compute the function call's stack space and register
requirements.
Pass 2: Replay the same computation but this time also write the
values out to the target. */
for (write_pass = 0; write_pass < 2; write_pass++)
{
int argno;
/* Next available floating point register for float and double
arguments. */
int freg = 1;
/* Next available general register for non-vector (but possibly
float) arguments. */
int greg = 3;
/* Next available vector register for vector arguments. */
int vreg = 2;
/* The address, at which the next general purpose parameter
(integer, struct, float, ...) should be saved. */
CORE_ADDR gparam;
/* Address, at which the next Altivec vector parameter should be
saved. */
CORE_ADDR vparam;
if (!write_pass)
{
/* During the first pass, GPARAM and VPARAM are more like
offsets (start address zero) than addresses. That way
the accumulate the total stack space each region
requires. */
gparam = 0;
vparam = 0;
}
else
{
/* Decrement the stack pointer making space for the Altivec
and general on-stack parameters. Set vparam and gparam
to their corresponding regions. */
vparam = align_down (sp - vparam_size, 16);
gparam = align_down (vparam - gparam_size, 16);
/* Add in space for the TOC, link editor double word,
compiler double word, LR save area, CR save area. */
sp = align_down (gparam - 48, 16);
}
/* If the function is returning a `struct', then there is an
extra hidden parameter (which will be passed in r3)
containing the address of that struct.. In that case we
should advance one word and start from r4 register to copy
parameters. This also consumes one on-stack parameter slot. */
if (struct_return)
{
if (write_pass)
regcache_cooked_write_signed (regcache,
tdep->ppc_gp0_regnum + greg,
struct_addr);
greg++;
gparam = align_up (gparam + tdep->wordsize, tdep->wordsize);
}
for (argno = 0; argno < nargs; argno++)
{
struct value *arg = args[argno];
struct type *type = check_typedef (value_type (arg));
const bfd_byte *val = value_contents (arg);
if (TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) <= 8)
{
/* Floats and Doubles go in f1 .. f13. They also
consume a left aligned GREG,, and can end up in
memory. */
if (write_pass)
{
if (ppc_floating_point_unit_p (current_gdbarch)
&& freg <= 13)
{
gdb_byte regval[MAX_REGISTER_SIZE];
struct type *regtype
= register_type (gdbarch, tdep->ppc_fp0_regnum);
convert_typed_floating (val, type, regval, regtype);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
regval);
}
if (greg <= 10)
{
/* The ABI states "Single precision floating
point values are mapped to the first word in
a single doubleword" and "... floating point
values mapped to the first eight doublewords
of the parameter save area are also passed in
general registers").
This code interprets that to mean: store it,
left aligned, in the general register. */
gdb_byte regval[MAX_REGISTER_SIZE];
memset (regval, 0, sizeof regval);
memcpy (regval, val, TYPE_LENGTH (type));
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg,
regval);
}
write_memory (gparam, val, TYPE_LENGTH (type));
}
/* Always consume parameter stack space. */
freg++;
greg++;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else if (TYPE_LENGTH (type) == 16 && TYPE_VECTOR (type)
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& tdep->ppc_vr0_regnum >= 0)
{
/* In the Altivec ABI, vectors go in the vector
registers v2 .. v13, or when that runs out, a vector
annex which goes above all the normal parameters.
NOTE: cagney/2003-09-21: This is a guess based on the
PowerOpen Altivec ABI. */
if (vreg <= 13)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_vr0_regnum + vreg, val);
vreg++;
}
else
{
if (write_pass)
write_memory (vparam, val, TYPE_LENGTH (type));
vparam = align_up (vparam + TYPE_LENGTH (type), 16);
}
}
else if ((TYPE_CODE (type) == TYPE_CODE_INT
|| TYPE_CODE (type) == TYPE_CODE_ENUM
|| TYPE_CODE (type) == TYPE_CODE_PTR)
&& TYPE_LENGTH (type) <= 8)
{
/* Scalars and Pointers get sign[un]extended and go in
gpr3 .. gpr10. They can also end up in memory. */
if (write_pass)
{
/* Sign extend the value, then store it unsigned. */
ULONGEST word = unpack_long (type, val);
/* Convert any function code addresses into
descriptors. */
if (TYPE_CODE (type) == TYPE_CODE_PTR
&& TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
{
CORE_ADDR desc = word;
convert_code_addr_to_desc_addr (word, &desc);
word = desc;
}
if (greg <= 10)
regcache_cooked_write_unsigned (regcache,
tdep->ppc_gp0_regnum +
greg, word);
write_memory_unsigned_integer (gparam, tdep->wordsize,
word);
}
greg++;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else
{
int byte;
for (byte = 0; byte < TYPE_LENGTH (type);
byte += tdep->wordsize)
{
if (write_pass && greg <= 10)
{
gdb_byte regval[MAX_REGISTER_SIZE];
int len = TYPE_LENGTH (type) - byte;
if (len > tdep->wordsize)
len = tdep->wordsize;
memset (regval, 0, sizeof regval);
/* WARNING: cagney/2003-09-21: As best I can
tell, the ABI specifies that the value should
be left aligned. Unfortunately, GCC doesn't
do this - it instead right aligns even sized
values and puts odd sized values on the
stack. Work around that by putting both a
left and right aligned value into the
register (hopefully no one notices :-^).
Arrrgh! */
/* Left aligned (8 byte values such as pointers
fill the buffer). */
memcpy (regval, val + byte, len);
/* Right aligned (but only if even). */
if (len == 1 || len == 2 || len == 4)
memcpy (regval + tdep->wordsize - len,
val + byte, len);
regcache_cooked_write (regcache, greg, regval);
}
greg++;
}
if (write_pass)
/* WARNING: cagney/2003-09-21: Strictly speaking, this
isn't necessary, unfortunately, GCC appears to get
"struct convention" parameter passing wrong putting
odd sized structures in memory instead of in a
register. Work around this by always writing the
value to memory. Fortunately, doing this
simplifies the code. */
write_memory (gparam, val, TYPE_LENGTH (type));
if (write_pass)
/* WARNING: cagney/2004-06-20: It appears that GCC
likes to put structures containing a single
floating-point member in an FP register instead of
general general purpose. */
/* Always consume parameter stack space. */
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
}
if (!write_pass)
{
/* Save the true region sizes ready for the second pass. */
vparam_size = vparam;
/* Make certain that the general parameter save area is at
least the minimum 8 registers (or doublewords) in size. */
if (greg < 8)
gparam_size = 8 * tdep->wordsize;
else
gparam_size = gparam;
}
}
/* Update %sp. */
regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
/* Write the backchain (it occupies WORDSIZED bytes). */
write_memory_signed_integer (sp, tdep->wordsize, back_chain);
/* Point the inferior function call's return address at the dummy's
breakpoint. */
regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
/* Use the func_addr to find the descriptor, and use that to find
the TOC. */
{
CORE_ADDR desc_addr;
if (convert_code_addr_to_desc_addr (func_addr, &desc_addr))
{
/* The TOC is the second double word in the descriptor. */
CORE_ADDR toc =
read_memory_unsigned_integer (desc_addr + tdep->wordsize,
tdep->wordsize);
regcache_cooked_write_unsigned (regcache,
tdep->ppc_gp0_regnum + 2, toc);
}
}
return sp;
}
CORE_ADDR
ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
CORE_ADDR func_addr = find_function_addr (function, NULL);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST back_chain;
/* See for-loop comment below. */
int write_pass;
/* Size of the Altivec's vector parameter region, the final value is
computed in the for-loop below. */
LONGEST vparam_size = 0;
/* Size of the general parameter region, the final value is computed
in the for-loop below. */
LONGEST gparam_size = 0;
/* Kevin writes ... I don't mind seeing tdep->wordsize used in the
calls to align_up(), align_down(), etc. because this makes it
easier to reuse this code (in a copy/paste sense) in the future,
but it is a 64-bit ABI and asserting that the wordsize is 8 bytes
at some point makes it easier to verify that this function is
correct without having to do a non-local analysis to figure out
the possible values of tdep->wordsize. */
gdb_assert (tdep->wordsize == 8);
/* This function exists to support a calling convention that
requires floating-point registers. It shouldn't be used on
processors that lack them. */
gdb_assert (ppc_floating_point_unit_p (gdbarch));
/* By this stage in the proceedings, SP has been decremented by "red
zone size" + "struct return size". Fetch the stack-pointer from
before this and use that as the BACK_CHAIN. */
regcache_cooked_read_unsigned (regcache, gdbarch_sp_regnum (gdbarch),
&back_chain);
/* Go through the argument list twice.
Pass 1: Compute the function call's stack space and register
requirements.
Pass 2: Replay the same computation but this time also write the
values out to the target. */
for (write_pass = 0; write_pass < 2; write_pass++)
{
int argno;
/* Next available floating point register for float and double
arguments. */
int freg = 1;
/* Next available general register for non-vector (but possibly
float) arguments. */
int greg = 3;
/* Next available vector register for vector arguments. */
int vreg = 2;
/* The address, at which the next general purpose parameter
(integer, struct, float, ...) should be saved. */
CORE_ADDR gparam;
/* Address, at which the next Altivec vector parameter should be
saved. */
CORE_ADDR vparam;
if (!write_pass)
{
/* During the first pass, GPARAM and VPARAM are more like
offsets (start address zero) than addresses. That way
they accumulate the total stack space each region
requires. */
gparam = 0;
vparam = 0;
}
else
{
/* Decrement the stack pointer making space for the Altivec
and general on-stack parameters. Set vparam and gparam
to their corresponding regions. */
vparam = align_down (sp - vparam_size, 16);
gparam = align_down (vparam - gparam_size, 16);
/* Add in space for the TOC, link editor double word,
compiler double word, LR save area, CR save area. */
sp = align_down (gparam - 48, 16);
}
/* If the function is returning a `struct', then there is an
extra hidden parameter (which will be passed in r3)
containing the address of that struct.. In that case we
should advance one word and start from r4 register to copy
parameters. This also consumes one on-stack parameter slot. */
if (struct_return)
{
if (write_pass)
regcache_cooked_write_signed (regcache,
tdep->ppc_gp0_regnum + greg,
struct_addr);
greg++;
gparam = align_up (gparam + tdep->wordsize, tdep->wordsize);
}
for (argno = 0; argno < nargs; argno++)
{
struct value *arg = args[argno];
struct type *type = check_typedef (value_type (arg));
const bfd_byte *val = value_contents (arg);
if (TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) <= 8)
{
/* Floats and Doubles go in f1 .. f13. They also
consume a left aligned GREG,, and can end up in
memory. */
if (write_pass)
{
gdb_byte regval[MAX_REGISTER_SIZE];
const gdb_byte *p;
/* Version 1.7 of the 64-bit PowerPC ELF ABI says:
"Single precision floating point values are mapped to
the first word in a single doubleword."
And version 1.9 says:
"Single precision floating point values are mapped to
the second word in a single doubleword."
GDB then writes single precision floating point values
at both words in a doubleword, to support both ABIs. */
if (TYPE_LENGTH (type) == 4)
{
memcpy (regval, val, 4);
memcpy (regval + 4, val, 4);
p = regval;
}
else
p = val;
/* Write value in the stack's parameter save area. */
write_memory (gparam, p, 8);
if (freg <= 13)
{
struct type *regtype
= register_type (gdbarch, tdep->ppc_fp0_regnum);
convert_typed_floating (val, type, regval, regtype);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
regval);
}
if (greg <= 10)
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg,
regval);
}
freg++;
greg++;
/* Always consume parameter stack space. */
gparam = align_up (gparam + 8, tdep->wordsize);
}
else if (TYPE_CODE (type) == TYPE_CODE_FLT
&& TYPE_LENGTH (type) == 16
&& (gdbarch_long_double_format (gdbarch)
== floatformats_ibm_long_double))
{
/* IBM long double stored in two doublewords of the
parameter save area and corresponding registers. */
if (write_pass)
{
if (!tdep->soft_float && freg <= 13)
{
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
val);
if (freg <= 12)
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg + 1,
val + 8);
}
if (greg <= 10)
{
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg,
val);
if (greg <= 9)
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 1,
val + 8);
}
write_memory (gparam, val, TYPE_LENGTH (type));
}
freg += 2;
greg += 2;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else if (TYPE_CODE (type) == TYPE_CODE_DECFLOAT
&& TYPE_LENGTH (type) <= 8)
{
/* 32-bit and 64-bit decimal floats go in f1 .. f13. They can
end up in memory. */
if (write_pass)
{
gdb_byte regval[MAX_REGISTER_SIZE];
const gdb_byte *p;
/* 32-bit decimal floats are right aligned in the
doubleword. */
if (TYPE_LENGTH (type) == 4)
{
memcpy (regval + 4, val, 4);
p = regval;
}
else
p = val;
/* Write value in the stack's parameter save area. */
write_memory (gparam, p, 8);
if (freg <= 13)
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg, p);
}
freg++;
greg++;
/* Always consume parameter stack space. */
gparam = align_up (gparam + 8, tdep->wordsize);
}
else if (TYPE_CODE (type) == TYPE_CODE_DECFLOAT &&
TYPE_LENGTH (type) == 16)
{
/* 128-bit decimal floats go in f2 .. f12, always in even/odd
pairs. They can end up in memory, using two doublewords. */
if (write_pass)
{
if (freg <= 12)
{
/* Make sure freg is even. */
freg += freg & 1;
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg, val);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg + 1, val + 8);
}
write_memory (gparam, val, TYPE_LENGTH (type));
}
freg += 2;
greg += 2;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else if (TYPE_LENGTH (type) == 16 && TYPE_VECTOR (type)
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& tdep->ppc_vr0_regnum >= 0)
{
/* In the Altivec ABI, vectors go in the vector
registers v2 .. v13, or when that runs out, a vector
annex which goes above all the normal parameters.
NOTE: cagney/2003-09-21: This is a guess based on the
PowerOpen Altivec ABI. */
if (vreg <= 13)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_vr0_regnum + vreg, val);
vreg++;
}
else
{
if (write_pass)
write_memory (vparam, val, TYPE_LENGTH (type));
vparam = align_up (vparam + TYPE_LENGTH (type), 16);
}
}
else if ((TYPE_CODE (type) == TYPE_CODE_INT
|| TYPE_CODE (type) == TYPE_CODE_ENUM
|| TYPE_CODE (type) == TYPE_CODE_BOOL
|| TYPE_CODE (type) == TYPE_CODE_CHAR
|| TYPE_CODE (type) == TYPE_CODE_PTR
|| TYPE_CODE (type) == TYPE_CODE_REF)
&& TYPE_LENGTH (type) <= 8)
{
/* Scalars and Pointers get sign[un]extended and go in
gpr3 .. gpr10. They can also end up in memory. */
if (write_pass)
{
/* Sign extend the value, then store it unsigned. */
ULONGEST word = unpack_long (type, val);
/* Convert any function code addresses into
descriptors. */
if (TYPE_CODE (type) == TYPE_CODE_PTR
|| TYPE_CODE (type) == TYPE_CODE_REF)
{
struct type *target_type;
target_type = check_typedef (TYPE_TARGET_TYPE (type));
if (TYPE_CODE (target_type) == TYPE_CODE_FUNC
|| TYPE_CODE (target_type) == TYPE_CODE_METHOD)
{
CORE_ADDR desc = word;
convert_code_addr_to_desc_addr (word, &desc);
word = desc;
}
}
if (greg <= 10)
regcache_cooked_write_unsigned (regcache,
tdep->ppc_gp0_regnum +
greg, word);
write_memory_unsigned_integer (gparam, tdep->wordsize,
byte_order, word);
}
greg++;
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
else
{
int byte;
for (byte = 0; byte < TYPE_LENGTH (type);
byte += tdep->wordsize)
{
if (write_pass && greg <= 10)
{
gdb_byte regval[MAX_REGISTER_SIZE];
int len = TYPE_LENGTH (type) - byte;
if (len > tdep->wordsize)
len = tdep->wordsize;
memset (regval, 0, sizeof regval);
/* The ABI (version 1.9) specifies that values
smaller than one doubleword are right-aligned
and those larger are left-aligned. GCC
versions before 3.4 implemented this
incorrectly; see
<http://gcc.gnu.org/gcc-3.4/powerpc-abi.html>. */
if (byte == 0)
memcpy (regval + tdep->wordsize - len,
val + byte, len);
else
memcpy (regval, val + byte, len);
regcache_cooked_write (regcache, greg, regval);
}
greg++;
}
if (write_pass)
{
/* WARNING: cagney/2003-09-21: Strictly speaking, this
isn't necessary, unfortunately, GCC appears to get
"struct convention" parameter passing wrong putting
odd sized structures in memory instead of in a
register. Work around this by always writing the
value to memory. Fortunately, doing this
simplifies the code. */
int len = TYPE_LENGTH (type);
if (len < tdep->wordsize)
write_memory (gparam + tdep->wordsize - len, val, len);
else
write_memory (gparam, val, len);
}
if (freg <= 13
&& TYPE_CODE (type) == TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type) == 1
&& TYPE_LENGTH (type) <= 16)
{
/* The ABI (version 1.9) specifies that structs
containing a single floating-point value, at any
level of nesting of single-member structs, are
passed in floating-point registers. */
while (TYPE_CODE (type) == TYPE_CODE_STRUCT
&& TYPE_NFIELDS (type) == 1)
type = check_typedef (TYPE_FIELD_TYPE (type, 0));
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
if (TYPE_LENGTH (type) <= 8)
{
if (write_pass)
{
gdb_byte regval[MAX_REGISTER_SIZE];
struct type *regtype
= register_type (gdbarch,
tdep->ppc_fp0_regnum);
convert_typed_floating (val, type, regval,
regtype);
regcache_cooked_write (regcache,
(tdep->ppc_fp0_regnum
+ freg),
regval);
}
freg++;
}
else if (TYPE_LENGTH (type) == 16
&& (gdbarch_long_double_format (gdbarch)
== floatformats_ibm_long_double))
{
if (write_pass)
{
regcache_cooked_write (regcache,
(tdep->ppc_fp0_regnum
+ freg),
val);
if (freg <= 12)
regcache_cooked_write (regcache,
(tdep->ppc_fp0_regnum
+ freg + 1),
val + 8);
}
freg += 2;
}
}
}
/* Always consume parameter stack space. */
gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
}
}
if (!write_pass)
{
/* Save the true region sizes ready for the second pass. */
vparam_size = vparam;
/* Make certain that the general parameter save area is at
least the minimum 8 registers (or doublewords) in size. */
if (greg < 8)
gparam_size = 8 * tdep->wordsize;
else
gparam_size = gparam;
}
}
/* Update %sp. */
regcache_cooked_write_signed (regcache, gdbarch_sp_regnum (gdbarch), sp);
/* Write the backchain (it occupies WORDSIZED bytes). */
write_memory_signed_integer (sp, tdep->wordsize, byte_order, back_chain);
/* Point the inferior function call's return address at the dummy's
breakpoint. */
regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
/* Use the func_addr to find the descriptor, and use that to find
the TOC. If we're calling via a function pointer, the pointer
itself identifies the descriptor. */
{
struct type *ftype = check_typedef (value_type (function));
CORE_ADDR desc_addr = value_as_address (function);
if (TYPE_CODE (ftype) == TYPE_CODE_PTR
|| convert_code_addr_to_desc_addr (func_addr, &desc_addr))
{
/* The TOC is the second double word in the descriptor. */
CORE_ADDR toc =
read_memory_unsigned_integer (desc_addr + tdep->wordsize,
tdep->wordsize, byte_order);
regcache_cooked_write_unsigned (regcache,
tdep->ppc_gp0_regnum + 2, toc);
}
}
return sp;
}
CORE_ADDR
ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST saved_sp;
int argspace = 0; /* 0 is an initial wrong guess. */
int write_pass;
gdb_assert (tdep->wordsize == 4);
regcache_cooked_read_unsigned (regcache, gdbarch_sp_regnum (gdbarch),
&saved_sp);
/* Go through the argument list twice.
Pass 1: Figure out how much new stack space is required for
arguments and pushed values. Unlike the PowerOpen ABI, the SysV
ABI doesn't reserve any extra space for parameters which are put
in registers, but does always push structures and then pass their
address.
Pass 2: Replay the same computation but this time also write the
values out to the target. */
for (write_pass = 0; write_pass < 2; write_pass++)
{
int argno;
/* Next available floating point register for float and double
arguments. */
int freg = 1;
/* Next available general register for non-float, non-vector
arguments. */
int greg = 3;
/* Next available vector register for vector arguments. */
int vreg = 2;
/* Arguments start above the "LR save word" and "Back chain". */
int argoffset = 2 * tdep->wordsize;
/* Structures start after the arguments. */
int structoffset = argoffset + argspace;
/* If the function is returning a `struct', then the first word
(which will be passed in r3) is used for struct return
address. In that case we should advance one word and start
from r4 register to copy parameters. */
if (struct_return)
{
if (write_pass)
regcache_cooked_write_signed (regcache,
tdep->ppc_gp0_regnum + greg,
struct_addr);
greg++;
}
for (argno = 0; argno < nargs; argno++)
{
struct value *arg = args[argno];
struct type *type = check_typedef (value_type (arg));
int len = TYPE_LENGTH (type);
const bfd_byte *val = value_contents (arg);
if (TYPE_CODE (type) == TYPE_CODE_FLT && len <= 8
&& !tdep->soft_float)
{
/* Floating point value converted to "double" then
passed in an FP register, when the registers run out,
8 byte aligned stack is used. */
if (freg <= 8)
{
if (write_pass)
{
/* Always store the floating point value using
the register's floating-point format. */
gdb_byte regval[MAX_REGISTER_SIZE];
struct type *regtype
= register_type (gdbarch, tdep->ppc_fp0_regnum + freg);
convert_typed_floating (val, type, regval, regtype);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
regval);
}
freg++;
}
else
{
/* The SysV ABI tells us to convert floats to
doubles before writing them to an 8 byte aligned
stack location. Unfortunately GCC does not do
that, and stores floats into 4 byte aligned
locations without converting them to doubles.
Since there is no know compiler that actually
follows the ABI here, we implement the GCC
convention. */
/* Align to 4 bytes or 8 bytes depending on the type of
the argument (float or double). */
argoffset = align_up (argoffset, len);
if (write_pass)
write_memory (sp + argoffset, val, len);
argoffset += len;
}
}
else if (TYPE_CODE (type) == TYPE_CODE_FLT
&& len == 16
&& !tdep->soft_float
&& (gdbarch_long_double_format (gdbarch)
== floatformats_ibm_long_double))
{
/* IBM long double passed in two FP registers if
available, otherwise 8-byte aligned stack. */
if (freg <= 7)
{
if (write_pass)
{
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
val);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg + 1,
val + 8);
}
freg += 2;
}
else
{
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, len);
argoffset += 16;
}
}
else if (len == 8
&& (TYPE_CODE (type) == TYPE_CODE_INT /* long long */
|| TYPE_CODE (type) == TYPE_CODE_FLT /* double */
|| (TYPE_CODE (type) == TYPE_CODE_DECFLOAT
&& tdep->soft_float)))
{
/* "long long" or soft-float "double" or "_Decimal64"
passed in an odd/even register pair with the low
addressed word in the odd register and the high
addressed word in the even register, or when the
registers run out an 8 byte aligned stack
location. */
if (greg > 9)
{
/* Just in case GREG was 10. */
greg = 11;
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, len);
argoffset += 8;
}
else
{
/* Must start on an odd register - r3/r4 etc. */
if ((greg & 1) == 0)
greg++;
if (write_pass)
{
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 0,
val + 0);
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 1,
val + 4);
}
greg += 2;
}
}
else if (len == 16
&& ((TYPE_CODE (type) == TYPE_CODE_FLT
&& (gdbarch_long_double_format (gdbarch)
== floatformats_ibm_long_double))
|| (TYPE_CODE (type) == TYPE_CODE_DECFLOAT
&& tdep->soft_float)))
{
/* Soft-float IBM long double or _Decimal128 passed in
four consecutive registers, or on the stack. The
registers are not necessarily odd/even pairs. */
if (greg > 7)
{
greg = 11;
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, len);
argoffset += 16;
}
else
{
if (write_pass)
{
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 0,
val + 0);
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 1,
val + 4);
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 2,
val + 8);
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 3,
val + 12);
}
greg += 4;
}
}
else if (TYPE_CODE (type) == TYPE_CODE_DECFLOAT && len <= 8
&& !tdep->soft_float)
{
/* 32-bit and 64-bit decimal floats go in f1 .. f8. They can
end up in memory. */
if (freg <= 8)
{
if (write_pass)
{
gdb_byte regval[MAX_REGISTER_SIZE];
const gdb_byte *p;
/* 32-bit decimal floats are right aligned in the
doubleword. */
if (TYPE_LENGTH (type) == 4)
{
memcpy (regval + 4, val, 4);
p = regval;
}
else
p = val;
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg, p);
}
freg++;
}
else
{
argoffset = align_up (argoffset, len);
if (write_pass)
/* Write value in the stack's parameter save area. */
write_memory (sp + argoffset, val, len);
argoffset += len;
}
}
else if (TYPE_CODE (type) == TYPE_CODE_DECFLOAT && len == 16
&& !tdep->soft_float)
{
/* 128-bit decimal floats go in f2 .. f7, always in even/odd
pairs. They can end up in memory, using two doublewords. */
if (freg <= 6)
{
/* Make sure freg is even. */
freg += freg & 1;
if (write_pass)
{
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg, val);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg + 1, val + 8);
}
}
else
{
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, 16);
argoffset += 16;
}
/* If a 128-bit decimal float goes to the stack because only f7
and f8 are free (thus there's no even/odd register pair
available), these registers should be marked as occupied.
Hence we increase freg even when writing to memory. */
freg += 2;
}
else if (len == 16
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type)
&& tdep->vector_abi == POWERPC_VEC_ALTIVEC)
{
/* Vector parameter passed in an Altivec register, or
when that runs out, 16 byte aligned stack location. */
if (vreg <= 13)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_vr0_regnum + vreg, val);
vreg++;
}
else
{
argoffset = align_up (argoffset, 16);
if (write_pass)
write_memory (sp + argoffset, val, 16);
argoffset += 16;
}
}
else if (len == 8
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type)
&& tdep->vector_abi == POWERPC_VEC_SPE)
{
/* Vector parameter passed in an e500 register, or when
that runs out, 8 byte aligned stack location. Note
that since e500 vector and general purpose registers
both map onto the same underlying register set, a
"greg" and not a "vreg" is consumed here. A cooked
write stores the value in the correct locations
within the raw register cache. */
if (greg <= 10)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_ev0_regnum + greg, val);
greg++;
}
else
{
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, 8);
argoffset += 8;
}
}
else
{
/* Reduce the parameter down to something that fits in a
"word". */
gdb_byte word[MAX_REGISTER_SIZE];
memset (word, 0, MAX_REGISTER_SIZE);
if (len > tdep->wordsize
|| TYPE_CODE (type) == TYPE_CODE_STRUCT
|| TYPE_CODE (type) == TYPE_CODE_UNION)
{
/* Structs and large values are put in an
aligned stack slot ... */
if (TYPE_CODE (type) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type)
&& len >= 16)
structoffset = align_up (structoffset, 16);
else
structoffset = align_up (structoffset, 8);
if (write_pass)
write_memory (sp + structoffset, val, len);
/* ... and then a "word" pointing to that address is
passed as the parameter. */
store_unsigned_integer (word, tdep->wordsize, byte_order,
sp + structoffset);
structoffset += len;
}
else if (TYPE_CODE (type) == TYPE_CODE_INT)
/* Sign or zero extend the "int" into a "word". */
store_unsigned_integer (word, tdep->wordsize, byte_order,
unpack_long (type, val));
else
/* Always goes in the low address. */
memcpy (word, val, len);
/* Store that "word" in a register, or on the stack.
The words have "4" byte alignment. */
if (greg <= 10)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg, word);
greg++;
}
else
{
argoffset = align_up (argoffset, tdep->wordsize);
if (write_pass)
write_memory (sp + argoffset, word, tdep->wordsize);
argoffset += tdep->wordsize;
}
}
}
/* Compute the actual stack space requirements. */
if (!write_pass)
{
/* Remember the amount of space needed by the arguments. */
argspace = argoffset;
/* Allocate space for both the arguments and the structures. */
sp -= (argoffset + structoffset);
/* Ensure that the stack is still 16 byte aligned. */
sp = align_down (sp, 16);
}
/* The psABI says that "A caller of a function that takes a
variable argument list shall set condition register bit 6 to
1 if it passes one or more arguments in the floating-point
registers. It is strongly recommended that the caller set the
bit to 0 otherwise..." Doing this for normal functions too
shouldn't hurt. */
if (write_pass)
{
ULONGEST cr;
regcache_cooked_read_unsigned (regcache, tdep->ppc_cr_regnum, &cr);
if (freg > 1)
cr |= 0x02000000;
else
cr &= ~0x02000000;
regcache_cooked_write_unsigned (regcache, tdep->ppc_cr_regnum, cr);
}
}
/* Update %sp. */
regcache_cooked_write_signed (regcache, gdbarch_sp_regnum (gdbarch), sp);
/* Write the backchain (it occupies WORDSIZED bytes). */
write_memory_signed_integer (sp, tdep->wordsize, byte_order, saved_sp);
/* Point the inferior function call's return address at the dummy's
breakpoint. */
regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
return sp;
}
CORE_ADDR
ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
const CORE_ADDR saved_sp = read_sp ();
int argspace = 0; /* 0 is an initial wrong guess. */
int write_pass;
/* Go through the argument list twice.
Pass 1: Figure out how much new stack space is required for
arguments and pushed values. Unlike the PowerOpen ABI, the SysV
ABI doesn't reserve any extra space for parameters which are put
in registers, but does always push structures and then pass their
address.
Pass 2: Replay the same computation but this time also write the
values out to the target. */
for (write_pass = 0; write_pass < 2; write_pass++)
{
int argno;
/* Next available floating point register for float and double
arguments. */
int freg = 1;
/* Next available general register for non-float, non-vector
arguments. */
int greg = 3;
/* Next available vector register for vector arguments. */
int vreg = 2;
/* Arguments start above the "LR save word" and "Back chain". */
int argoffset = 2 * tdep->wordsize;
/* Structures start after the arguments. */
int structoffset = argoffset + argspace;
/* If the function is returning a `struct', then the first word
(which will be passed in r3) is used for struct return
address. In that case we should advance one word and start
from r4 register to copy parameters. */
if (struct_return)
{
if (write_pass)
regcache_cooked_write_signed (regcache,
tdep->ppc_gp0_regnum + greg,
struct_addr);
greg++;
}
for (argno = 0; argno < nargs; argno++)
{
struct value *arg = args[argno];
struct type *type = check_typedef (VALUE_TYPE (arg));
int len = TYPE_LENGTH (type);
char *val = VALUE_CONTENTS (arg);
if (TYPE_CODE (type) == TYPE_CODE_FLT
&& ppc_floating_point_unit_p (current_gdbarch) && len <= 8)
{
/* Floating point value converted to "double" then
passed in an FP register, when the registers run out,
8 byte aligned stack is used. */
if (freg <= 8)
{
if (write_pass)
{
/* Always store the floating point value using
the register's floating-point format. */
char regval[MAX_REGISTER_SIZE];
struct type *regtype
= register_type (gdbarch, tdep->ppc_fp0_regnum + freg);
convert_typed_floating (val, type, regval, regtype);
regcache_cooked_write (regcache,
tdep->ppc_fp0_regnum + freg,
regval);
}
freg++;
}
else
{
/* SysV ABI converts floats to doubles before
writing them to an 8 byte aligned stack location. */
argoffset = align_up (argoffset, 8);
if (write_pass)
{
char memval[8];
struct type *memtype;
switch (TARGET_BYTE_ORDER)
{
case BFD_ENDIAN_BIG:
memtype = builtin_type_ieee_double_big;
break;
case BFD_ENDIAN_LITTLE:
memtype = builtin_type_ieee_double_little;
break;
default:
internal_error (__FILE__, __LINE__, "bad switch");
}
convert_typed_floating (val, type, memval, memtype);
write_memory (sp + argoffset, val, len);
}
argoffset += 8;
}
}
else if (len == 8 && (TYPE_CODE (type) == TYPE_CODE_INT /* long long */
|| (!ppc_floating_point_unit_p (current_gdbarch) && TYPE_CODE (type) == TYPE_CODE_FLT))) /* double */
{
/* "long long" or "double" passed in an odd/even
register pair with the low addressed word in the odd
register and the high addressed word in the even
register, or when the registers run out an 8 byte
aligned stack location. */
if (greg > 9)
{
/* Just in case GREG was 10. */
greg = 11;
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, len);
argoffset += 8;
}
else if (tdep->wordsize == 8)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg, val);
greg += 1;
}
else
{
/* Must start on an odd register - r3/r4 etc. */
if ((greg & 1) == 0)
greg++;
if (write_pass)
{
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 0,
val + 0);
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg + 1,
val + 4);
}
greg += 2;
}
}
else if (len == 16
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type) && tdep->ppc_vr0_regnum >= 0)
{
/* Vector parameter passed in an Altivec register, or
when that runs out, 16 byte aligned stack location. */
if (vreg <= 13)
{
if (write_pass)
regcache_cooked_write (current_regcache,
tdep->ppc_vr0_regnum + vreg, val);
vreg++;
}
else
{
argoffset = align_up (argoffset, 16);
if (write_pass)
write_memory (sp + argoffset, val, 16);
argoffset += 16;
}
}
else if (len == 8
&& TYPE_CODE (type) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type) && tdep->ppc_ev0_regnum >= 0)
{
/* Vector parameter passed in an e500 register, or when
that runs out, 8 byte aligned stack location. Note
that since e500 vector and general purpose registers
both map onto the same underlying register set, a
"greg" and not a "vreg" is consumed here. A cooked
write stores the value in the correct locations
within the raw register cache. */
if (greg <= 10)
{
if (write_pass)
regcache_cooked_write (current_regcache,
tdep->ppc_ev0_regnum + greg, val);
greg++;
}
else
{
argoffset = align_up (argoffset, 8);
if (write_pass)
write_memory (sp + argoffset, val, 8);
argoffset += 8;
}
}
else
{
/* Reduce the parameter down to something that fits in a
"word". */
char word[MAX_REGISTER_SIZE];
memset (word, 0, MAX_REGISTER_SIZE);
if (len > tdep->wordsize
|| TYPE_CODE (type) == TYPE_CODE_STRUCT
|| TYPE_CODE (type) == TYPE_CODE_UNION)
{
/* Structs and large values are put on an 8 byte
aligned stack ... */
structoffset = align_up (structoffset, 8);
if (write_pass)
write_memory (sp + structoffset, val, len);
/* ... and then a "word" pointing to that address is
passed as the parameter. */
store_unsigned_integer (word, tdep->wordsize,
sp + structoffset);
structoffset += len;
}
else if (TYPE_CODE (type) == TYPE_CODE_INT)
/* Sign or zero extend the "int" into a "word". */
store_unsigned_integer (word, tdep->wordsize,
unpack_long (type, val));
else
/* Always goes in the low address. */
memcpy (word, val, len);
/* Store that "word" in a register, or on the stack.
The words have "4" byte alignment. */
if (greg <= 10)
{
if (write_pass)
regcache_cooked_write (regcache,
tdep->ppc_gp0_regnum + greg, word);
greg++;
}
else
{
argoffset = align_up (argoffset, tdep->wordsize);
if (write_pass)
write_memory (sp + argoffset, word, tdep->wordsize);
argoffset += tdep->wordsize;
}
}
}
/* Compute the actual stack space requirements. */
if (!write_pass)
{
/* Remember the amount of space needed by the arguments. */
argspace = argoffset;
/* Allocate space for both the arguments and the structures. */
sp -= (argoffset + structoffset);
/* Ensure that the stack is still 16 byte aligned. */
sp = align_down (sp, 16);
}
}
/* Update %sp. */
regcache_cooked_write_signed (regcache, SP_REGNUM, sp);
/* Write the backchain (it occupies WORDSIZED bytes). */
write_memory_signed_integer (sp, tdep->wordsize, saved_sp);
/* Point the inferior function call's return address at the dummy's
breakpoint. */
regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
return sp;
}
/* Write given values into registers. The registers and values are
given as pairs. The corresponding MI command is
-data-write-register-values <format> [<regnum1> <value1>...<regnumN> <valueN>]*/
enum mi_cmd_result
mi_cmd_data_write_register_values (char *command, char **argv, int argc)
{
int numregs, i;
char format;
/* Note that the test for a valid register must include checking the
gdbarch_register_name because gdbarch_num_regs may be allocated for
the union of the register sets within a family of related processors.
In this case, some entries of gdbarch_register_name will change depending
upon the particular processor being debugged. */
numregs = gdbarch_num_regs (current_gdbarch)
+ gdbarch_num_pseudo_regs (current_gdbarch);
if (argc == 0)
{
mi_error_message = xstrprintf ("mi_cmd_data_write_register_values: Usage: -data-write-register-values <format> [<regnum1> <value1>...<regnumN> <valueN>]");
return MI_CMD_ERROR;
}
format = (int) argv[0][0];
if (!target_has_registers)
{
mi_error_message = xstrprintf ("mi_cmd_data_write_register_values: No registers.");
return MI_CMD_ERROR;
}
if (!(argc - 1))
{
mi_error_message = xstrprintf ("mi_cmd_data_write_register_values: No regs and values specified.");
return MI_CMD_ERROR;
}
if ((argc - 1) % 2)
{
mi_error_message = xstrprintf ("mi_cmd_data_write_register_values: Regs and vals are not in pairs.");
return MI_CMD_ERROR;
}
for (i = 1; i < argc; i = i + 2)
{
int regnum = atoi (argv[i]);
if (regnum >= 0 && regnum < numregs
&& gdbarch_register_name (current_gdbarch, regnum)
&& *gdbarch_register_name (current_gdbarch, regnum))
{
LONGEST value;
/* Get the value as a number. */
value = parse_and_eval_address (argv[i + 1]);
/* Write it down. */
regcache_cooked_write_signed (get_current_regcache (), regnum, value);
}
else
{
mi_error_message = xstrprintf ("bad register number");
return MI_CMD_ERROR;
}
}
return MI_CMD_DONE;
}
