int board_early_init_r(void) { /* * ICON has 64MBytes of NOR FLASH (Spansion 29GL512), but the * boot EBC mapping only supports a maximum of 16MBytes * (4.ff00.0000 - 4.ffff.ffff). * To solve this problem, the FLASH has to get remapped to another * EBC address which accepts bigger regions: * * 0xfc00.0000 -> 4.ec00.0000 */ /* Remap the NOR FLASH to 0xec00.0000 ... 0xefff.ffff */ mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); /* Remove TLB entry of boot EBC mapping */ remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); /* Add TLB entry for 0xfc00.0000 -> 0x4.ec00.0000 */ program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE); /* * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address * 0xfc00.0000 is possible */ /* * Clear potential errors resulting from auto-calibration. * If not done, then we could get an interrupt later on when * exceptions are enabled. */ set_mcsr(get_mcsr()); return 0; }
/*----------------------------------------------------------------------------- * Function: initdram * Description: Configures SDRAM memory banks for DDR operation. * Auto Memory Configuration option reads the DDR SDRAM EEPROMs * via the IIC bus and then configures the DDR SDRAM memory * banks appropriately. If Auto Memory Configuration is * not used, it is assumed that no DIMM is plugged *-----------------------------------------------------------------------------*/ phys_size_t initdram(int board_type) { unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; unsigned long dimm_ranks[MAXDIMMS]; unsigned long ranks; unsigned long rows; unsigned long banks; unsigned long cols; unsigned long width; unsigned long const sdram_freq = get_bus_freq(0); unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr); /* on board dimm banks */ unsigned long cas_latency = 0; /* to quiet initialization warning */ unsigned long dram_size; debug("\nEntering initdram()\n"); /*------------------------------------------------------------------ * Stop the DDR-SDRAM controller. *-----------------------------------------------------------------*/ mtsdram(DDR0_02, DDR0_02_START_ENCODE(0)); /* * Make sure I2C controller is initialized * before continuing. */ /* switch to correct I2C bus */ I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /*------------------------------------------------------------------ * Clear out the serial presence detect buffers. * Perform IIC reads from the dimm. Fill in the spds. * Check to see if the dimm slots are populated *-----------------------------------------------------------------*/ get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks); /*------------------------------------------------------------------ * Check the frequency supported for the dimms plugged. *-----------------------------------------------------------------*/ check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); /*------------------------------------------------------------------ * Check and get size information. *-----------------------------------------------------------------*/ get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks, &cols, &width); /*------------------------------------------------------------------ * Check the voltage type for the dimms plugged. *-----------------------------------------------------------------*/ check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks); /*------------------------------------------------------------------ * Program registers for SDRAM controller. *-----------------------------------------------------------------*/ mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) | DDR0_00_DLL_START_POINT_DECODE(0x0A)); mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) | DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) | DDR0_01_INT_MASK_ENCODE(0xFF)); program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, rows, &cas_latency); program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); /* * TODO: tFAW not found in SPD. Value of 13 taken from Sequoia * board SDRAM, but may be overly conservative. */ mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) | DDR0_07_TFAW_ENCODE(13) | DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) | DDR0_07_AREFRESH_ENCODE(0)); mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) | DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) | DDR0_08_DDRII_ENCODE(1)); mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) | DDR0_09_RTT_0_ENCODE(0x1) | DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) | DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20)); program_ddr0_10(dimm_ranks, ranks); program_ddr0_11(sdram_freq); mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3)); mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) | DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) | DDR0_14_REG_DIMM_ENABLE_ENCODE(0)); mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY)); mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) | DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) | DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) | DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY)); mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) | DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) | DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) | DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY)); mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) | DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) | DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) | DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS)); mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) | DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) | DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) | DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS)); program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width); mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) | DDR0_23_FWC_ENCODE(0)); program_ddr0_24(ranks); program_ddr0_26(sdram_freq); program_ddr0_27(sdram_freq); mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) | DDR0_28_EMRS2_DATA_ENCODE(0x0000)); mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000)); mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) | DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency)); program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, cols, banks); program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq); denali_sdram_register_dump(); dram_size = (width >= 64) ? 8 : 4; dram_size *= 1 << cols; dram_size *= banks; dram_size *= 1 << rows; dram_size *= ranks; debug("dram_size = %lu\n", dram_size); /* Start the SDRAM controler */ mtsdram(DDR0_02, DDR0_02_START_ENCODE(1)); denali_wait_for_dlllock(); #if defined(CONFIG_DDR_DATA_EYE) /* * Map the first 1 MiB of memory in the TLB, and perform the data eye * search. */ program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE); denali_core_search_data_eye(); denali_sdram_register_dump(); remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE); #endif #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0); sync(); /* Zero the memory */ debug("Zeroing SDRAM..."); #if defined(CONFIG_SYS_MEM_TOP_HIDE) dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE); #else #error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file #endif /* Write modified dcache lines back to memory */ clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE); debug("Completed\n"); sync(); remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size); #if defined(CONFIG_DDR_ECC) /* * If ECC is enabled, clear and enable interrupts */ if (is_ecc_enabled()) { u32 val; sync(); /* Clear error status */ mfsdram(DDR0_00, val); mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL); /* Set 'int_mask' parameter to functionnal value */ mfsdram(DDR0_01, val); mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF); #if defined(CONFIG_DDR_DATA_EYE) /* * Running denali_core_search_data_eye() when ECC is enabled * causes non-ECC machine checks. This clears them. */ print_mcsr(); mtspr(SPRN_MCSR, mfspr(SPRN_MCSR)); print_mcsr(); #endif sync(); } #endif /* defined(CONFIG_DDR_ECC) */ #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */ program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE); return dram_size; }
/************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ phys_size_t initdram (int board_type) { #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_LCD4_LWMON5) /* CL=4 */ mtsdram(DDR0_02, 0x00000000); mtsdram(DDR0_00, 0x0000190A); mtsdram(DDR0_01, 0x01000000); mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */ mtsdram(DDR0_04, 0x0B030300); mtsdram(DDR0_05, 0x02020308); mtsdram(DDR0_06, 0x0003C812); mtsdram(DDR0_07, 0x00090100); mtsdram(DDR0_08, 0x03c80001); mtsdram(DDR0_09, 0x00011D5F); mtsdram(DDR0_10, 0x00000100); mtsdram(DDR0_11, 0x000CC800); mtsdram(DDR0_12, 0x00000003); mtsdram(DDR0_14, 0x00000000); mtsdram(DDR0_17, 0x1e000000); mtsdram(DDR0_18, 0x1e1e1e1e); mtsdram(DDR0_19, 0x1e1e1e1e); mtsdram(DDR0_20, 0x0B0B0B0B); mtsdram(DDR0_21, 0x0B0B0B0B); #ifdef CONFIG_DDR_ECC mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */ #else mtsdram(DDR0_22, 0x00267F0B); #endif mtsdram(DDR0_23, 0x01000000); mtsdram(DDR0_24, 0x01010001); mtsdram(DDR0_26, 0x2D93028A); mtsdram(DDR0_27, 0x0784682B); mtsdram(DDR0_28, 0x00000080); mtsdram(DDR0_31, 0x00000000); mtsdram(DDR0_42, 0x01000008); mtsdram(DDR0_43, 0x050A0200); mtsdram(DDR0_44, 0x00000005); mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ denali_wait_for_dlllock(); #if defined(CONFIG_DDR_DATA_EYE) /* -----------------------------------------------------------+ * Perform data eye search if requested. * ----------------------------------------------------------*/ program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, TLB_WORD2_I_ENABLE); denali_core_search_data_eye(); remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20); #endif /* * Program tlb entries for this size (dynamic) */ program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE); #if defined(CONFIG_DDR_ECC) #if defined(CONFIG_4xx_DCACHE) /* * If ECC is enabled, initialize the parity bits. */ program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0); #else /* CONFIG_4xx_DCACHE */ /* * Setup 2nd TLB with same physical address but different virtual address * with cache enabled. This is done for fast ECC generation. */ program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); /* * If ECC is enabled, initialize the parity bits. */ program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); /* * Now after initialization (auto-calibration and ECC generation) * remove the TLB entries with caches enabled and program again with * desired cache functionality */ remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20); #endif /* CONFIG_4xx_DCACHE */ #endif /* CONFIG_DDR_ECC */ /* * Clear possible errors resulting from data-eye-search. * If not done, then we could get an interrupt later on when * exceptions are enabled. */ set_mcsr(get_mcsr()); #endif /* CONFIG_SPL_BUILD */ return (CONFIG_SYS_MBYTES_SDRAM << 20); }
int cache_post_test (int flags) { void *virt = (void *)CONFIG_SYS_POST_CACHE_ADDR; int ints; int res = 0; int tlb = -1; /* index to the victim TLB entry */ /* * All 44x variants deal with cache management differently * because they have the address translation always enabled. * The 40x ppc's don't use address translation in U-Boot at all, * so we have to distinguish here between 40x and 44x. */ #ifdef CONFIG_440 int word0, i; /* * Allocate a new TLB entry, since we are going to modify * the write-through and caching inhibited storage attributes. */ program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE, TLB_WORD2_I_ENABLE); /* Find the TLB entry */ for (i = 0;; i++) { if (i >= PPC4XX_TLB_SIZE) { printf ("Failed to program tlb entry\n"); return -1; } word0 = mftlb1(i); if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) { tlb = i; break; } } #endif ints = disable_interrupts (); WATCHDOG_RESET (); if (res == 0) res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE); WATCHDOG_RESET (); if (res == 0) res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE); WATCHDOG_RESET (); if (res == 0) res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE); WATCHDOG_RESET (); if (res == 0) res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE); WATCHDOG_RESET (); if (res == 0) res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE); WATCHDOG_RESET (); if (res == 0) res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE); if (ints) enable_interrupts (); #ifdef CONFIG_440 remove_tlb((u32)virt, CACHE_POST_SIZE); #endif return res; }
/*********************************************************************** * * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ long int initdram (int board_type) { unsigned int dram_size = 0; mtsdram(DDR0_02, 0x00000000); /* Values must be kept in sync with Excel-table <<A0001492.>> ! */ mtsdram(DDR0_00, 0x0000190A); mtsdram(DDR0_01, 0x01000000); mtsdram(DDR0_03, 0x02030602); mtsdram(DDR0_04, 0x0A020200); mtsdram(DDR0_05, 0x02020307); switch (in_be16((u16 *)HCU_HW_VERSION_REGISTER) & HCU_HW_SDRAM_CONFIG_MASK) { case 1: dram_size = 256 * 1024 * 1024 ; mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */ mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */ mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */ break; case 0: default: dram_size = 128 * 1024 * 1024 ; mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */ mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */ mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */ break; } mtsdram(DDR0_07, 0x00090100); /* * TCPD=200 cycles of clock input is required to lock the DLL. * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001); */ mtsdram(DDR0_08, 0x02C80001); mtsdram(DDR0_09, 0x00011D5F); mtsdram(DDR0_10, 0x00000100); mtsdram(DDR0_12, 0x00000003); mtsdram(DDR0_14, 0x00000000); mtsdram(DDR0_17, 0x1D000000); mtsdram(DDR0_18, 0x1D1D1D1D); mtsdram(DDR0_19, 0x1D1D1D1D); mtsdram(DDR0_20, 0x0B0B0B0B); mtsdram(DDR0_21, 0x0B0B0B0B); #ifdef CONFIG_DDR_ECC mtsdram(DDR0_22, ECC_RAM); #else mtsdram(DDR0_22, NO_ECC_RAM); #endif mtsdram(DDR0_23, 0x00000000); mtsdram(DDR0_24, 0x01020001); mtsdram(DDR0_26, 0x2D930517); mtsdram(DDR0_27, 0x00008236); mtsdram(DDR0_28, 0x00000000); mtsdram(DDR0_31, 0x00000000); mtsdram(DDR0_42, 0x01000006); mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); wait_for_dlllock(); mtsdram(DDR0_00, 0x40000000); /* Zero init bit */ /* * Program tlb entries for this size (dynamic) */ remove_tlb(CFG_SDRAM_BASE, 256 << 20); program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE); /* * Setup 2nd TLB with same physical address but different virtual * address with cache enabled. This is done for fast ECC generation. */ program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0); #ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. */ program_ecc(CFG_DDR_CACHED_ADDR, dram_size); #endif return (dram_size); }