static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar)
{
struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
if (!IS_ERR_OR_NULL(ar_ahb->core_cold_rst))
reset_control_put(ar_ahb->core_cold_rst);
if (!IS_ERR_OR_NULL(ar_ahb->radio_cold_rst))
reset_control_put(ar_ahb->radio_cold_rst);
if (!IS_ERR_OR_NULL(ar_ahb->radio_warm_rst))
reset_control_put(ar_ahb->radio_warm_rst);
if (!IS_ERR_OR_NULL(ar_ahb->radio_srif_rst))
reset_control_put(ar_ahb->radio_srif_rst);
if (!IS_ERR_OR_NULL(ar_ahb->cpu_init_rst))
reset_control_put(ar_ahb->cpu_init_rst);
ar_ahb->core_cold_rst = NULL;
ar_ahb->radio_cold_rst = NULL;
ar_ahb->radio_warm_rst = NULL;
ar_ahb->radio_srif_rst = NULL;
ar_ahb->cpu_init_rst = NULL;
}
static int dwc3_of_simple_remove(struct platform_device *pdev)
{
struct dwc3_of_simple *simple = platform_get_drvdata(pdev);
struct device *dev = &pdev->dev;
int i;
of_platform_depopulate(dev);
for (i = 0; i < simple->num_clocks; i++) {
clk_disable_unprepare(simple->clks[i]);
clk_put(simple->clks[i]);
}
simple->num_clocks = 0;
if (!simple->pulse_resets)
reset_control_assert(simple->resets);
reset_control_put(simple->resets);
pm_runtime_disable(dev);
pm_runtime_put_noidle(dev);
pm_runtime_set_suspended(dev);
return 0;
}
static void gswip_gphy_fw_remove(struct gswip_priv *priv,
struct gswip_gphy_fw *gphy_fw)
{
int ret;
/* check if the device was fully probed */
if (!gphy_fw->fw_name)
return;
ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0);
if (ret)
dev_err(priv->dev, "can not reset GPHY FW pointer");
clk_disable_unprepare(gphy_fw->clk_gate);
reset_control_put(gphy_fw->reset);
}
/*
* The 1st USB controller contains some UTMI pad registers that are global for
* all the controllers on the chip. Those registers are also cleared when
* reset is asserted to the 1st controller. This means that the 1st controller
* can only be reset when no other controlled has finished probing. So we'll
* reset the 1st controller before doing any other setup on any of the
* controllers, and then never again.
*
* Since this is a PHY issue, the Tegra PHY driver should probably be doing
* the resetting of the USB controllers. But to keep compatibility with old
* device trees that don't have reset phandles in the PHYs, do it here.
* Those old DTs will be vulnerable to total USB breakage if the 1st EHCI
* device isn't the first one to finish probing, so warn them.
*/
static int tegra_reset_usb_controller(struct platform_device *pdev)
{
struct device_node *phy_np;
struct usb_hcd *hcd = platform_get_drvdata(pdev);
struct tegra_ehci_hcd *tegra =
(struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
if (!phy_np)
return -ENOENT;
if (!usb1_reset_attempted) {
struct reset_control *usb1_reset;
usb1_reset = of_reset_control_get(phy_np, "usb");
if (IS_ERR(usb1_reset)) {
dev_warn(&pdev->dev,
"can't get utmi-pads reset from the PHY\n");
dev_warn(&pdev->dev,
"continuing, but please update your DT\n");
} else {
reset_control_assert(usb1_reset);
udelay(1);
reset_control_deassert(usb1_reset);
}
reset_control_put(usb1_reset);
usb1_reset_attempted = true;
}
if (!of_property_read_bool(phy_np, "nvidia,has-utmi-pad-registers")) {
reset_control_assert(tegra->rst);
udelay(1);
reset_control_deassert(tegra->rst);
}
of_node_put(phy_np);
return 0;
}
static int dwc3_of_simple_probe(struct platform_device *pdev)
{
struct dwc3_of_simple *simple;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
int ret;
int i;
bool shared_resets = false;
simple = devm_kzalloc(dev, sizeof(*simple), GFP_KERNEL);
if (!simple)
return -ENOMEM;
platform_set_drvdata(pdev, simple);
simple->dev = dev;
/*
* Some controllers need to toggle the usb3-otg reset before trying to
* initialize the PHY, otherwise the PHY times out.
*/
if (of_device_is_compatible(np, "rockchip,rk3399-dwc3"))
simple->need_reset = true;
if (of_device_is_compatible(np, "amlogic,meson-axg-dwc3") ||
of_device_is_compatible(np, "amlogic,meson-gxl-dwc3")) {
shared_resets = true;
simple->pulse_resets = true;
}
simple->resets = of_reset_control_array_get(np, shared_resets, true);
if (IS_ERR(simple->resets)) {
ret = PTR_ERR(simple->resets);
dev_err(dev, "failed to get device resets, err=%d\n", ret);
return ret;
}
if (simple->pulse_resets) {
ret = reset_control_reset(simple->resets);
if (ret)
goto err_resetc_put;
} else {
ret = reset_control_deassert(simple->resets);
if (ret)
goto err_resetc_put;
}
ret = dwc3_of_simple_clk_init(simple, of_count_phandle_with_args(np,
"clocks", "#clock-cells"));
if (ret)
goto err_resetc_assert;
ret = of_platform_populate(np, NULL, NULL, dev);
if (ret) {
for (i = 0; i < simple->num_clocks; i++) {
clk_disable_unprepare(simple->clks[i]);
clk_put(simple->clks[i]);
}
goto err_resetc_assert;
}
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
return 0;
err_resetc_assert:
if (!simple->pulse_resets)
reset_control_assert(simple->resets);
err_resetc_put:
reset_control_put(simple->resets);
return ret;
}
static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar)
{
struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
struct device *dev;
int ret;
dev = &ar_ahb->pdev->dev;
ar_ahb->core_cold_rst = reset_control_get(dev, "wifi_core_cold");
if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst)) {
ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n",
PTR_ERR(ar_ahb->core_cold_rst));
ret = ar_ahb->core_cold_rst ?
PTR_ERR(ar_ahb->core_cold_rst) : -ENODEV;
goto out;
}
ar_ahb->radio_cold_rst = reset_control_get(dev, "wifi_radio_cold");
if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst)) {
ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n",
PTR_ERR(ar_ahb->radio_cold_rst));
ret = ar_ahb->radio_cold_rst ?
PTR_ERR(ar_ahb->radio_cold_rst) : -ENODEV;
goto err_core_cold_rst_put;
}
ar_ahb->radio_warm_rst = reset_control_get(dev, "wifi_radio_warm");
if (IS_ERR_OR_NULL(ar_ahb->radio_warm_rst)) {
ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n",
PTR_ERR(ar_ahb->radio_warm_rst));
ret = ar_ahb->radio_warm_rst ?
PTR_ERR(ar_ahb->radio_warm_rst) : -ENODEV;
goto err_radio_cold_rst_put;
}
ar_ahb->radio_srif_rst = reset_control_get(dev, "wifi_radio_srif");
if (IS_ERR_OR_NULL(ar_ahb->radio_srif_rst)) {
ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n",
PTR_ERR(ar_ahb->radio_srif_rst));
ret = ar_ahb->radio_srif_rst ?
PTR_ERR(ar_ahb->radio_srif_rst) : -ENODEV;
goto err_radio_warm_rst_put;
}
ar_ahb->cpu_init_rst = reset_control_get(dev, "wifi_cpu_init");
if (IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) {
ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n",
PTR_ERR(ar_ahb->cpu_init_rst));
ret = ar_ahb->cpu_init_rst ?
PTR_ERR(ar_ahb->cpu_init_rst) : -ENODEV;
goto err_radio_srif_rst_put;
}
return 0;
err_radio_srif_rst_put:
reset_control_put(ar_ahb->radio_srif_rst);
err_radio_warm_rst_put:
reset_control_put(ar_ahb->radio_warm_rst);
err_radio_cold_rst_put:
reset_control_put(ar_ahb->radio_cold_rst);
err_core_cold_rst_put:
reset_control_put(ar_ahb->core_cold_rst);
out:
return ret;
}
static int tegra30_ahub_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
const struct tegra30_ahub_soc_data *soc_data;
struct reset_control *rst;
int i;
struct resource *res0, *res1;
void __iomem *regs_apbif, *regs_ahub;
int ret = 0;
if (ahub)
return -ENODEV;
match = of_match_device(tegra30_ahub_of_match, &pdev->dev);
if (!match)
return -EINVAL;
soc_data = match->data;
/*
* The AHUB hosts a register bus: the "configlink". For this to
* operate correctly, all devices on this bus must be out of reset.
* Ensure that here.
*/
for (i = 0; i < ARRAY_SIZE(configlink_mods); i++) {
if (!(configlink_mods[i].mod_list_mask &
soc_data->mod_list_mask))
continue;
rst = reset_control_get_exclusive(&pdev->dev,
configlink_mods[i].rst_name);
if (IS_ERR(rst)) {
dev_err(&pdev->dev, "Can't get reset %s\n",
configlink_mods[i].rst_name);
ret = PTR_ERR(rst);
return ret;
}
ret = reset_control_deassert(rst);
reset_control_put(rst);
if (ret)
return ret;
}
ahub = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_ahub),
GFP_KERNEL);
if (!ahub)
return -ENOMEM;
dev_set_drvdata(&pdev->dev, ahub);
ahub->soc_data = soc_data;
ahub->dev = &pdev->dev;
ahub->clk_d_audio = devm_clk_get(&pdev->dev, "d_audio");
if (IS_ERR(ahub->clk_d_audio)) {
dev_err(&pdev->dev, "Can't retrieve ahub d_audio clock\n");
ret = PTR_ERR(ahub->clk_d_audio);
return ret;
}
ahub->clk_apbif = devm_clk_get(&pdev->dev, "apbif");
if (IS_ERR(ahub->clk_apbif)) {
dev_err(&pdev->dev, "Can't retrieve ahub apbif clock\n");
ret = PTR_ERR(ahub->clk_apbif);
return ret;
}
res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs_apbif = devm_ioremap_resource(&pdev->dev, res0);
if (IS_ERR(regs_apbif))
return PTR_ERR(regs_apbif);
ahub->apbif_addr = res0->start;
ahub->regmap_apbif = devm_regmap_init_mmio(&pdev->dev, regs_apbif,
&tegra30_ahub_apbif_regmap_config);
if (IS_ERR(ahub->regmap_apbif)) {
dev_err(&pdev->dev, "apbif regmap init failed\n");
ret = PTR_ERR(ahub->regmap_apbif);
return ret;
}
regcache_cache_only(ahub->regmap_apbif, true);
res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
regs_ahub = devm_ioremap_resource(&pdev->dev, res1);
if (IS_ERR(regs_ahub))
return PTR_ERR(regs_ahub);
ahub->regmap_ahub = devm_regmap_init_mmio(&pdev->dev, regs_ahub,
&tegra30_ahub_ahub_regmap_config);
if (IS_ERR(ahub->regmap_ahub)) {
dev_err(&pdev->dev, "ahub regmap init failed\n");
ret = PTR_ERR(ahub->regmap_ahub);
return ret;
}
regcache_cache_only(ahub->regmap_ahub, true);
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = tegra30_ahub_runtime_resume(&pdev->dev);
if (ret)
goto err_pm_disable;
}
of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
return 0;
err_pm_disable:
pm_runtime_disable(&pdev->dev);
return ret;
}
static int nss_probe(struct platform_device *nss_dev)
#endif
{
struct nss_top_instance *nss_top = &nss_top_main;
struct nss_ctx_instance *nss_ctx = NULL;
struct nss_platform_data *npd = NULL;
struct netdev_priv_instance *ndev_priv;
#if (NSS_DT_SUPPORT == 1)
struct reset_control *rstctl = NULL;
#endif
int i, err = 0;
const struct firmware *nss_fw = NULL;
int rc = -ENODEV;
void __iomem *load_mem;
#if (NSS_DT_SUPPORT == 1)
struct device_node *np = NULL;
if (nss_top_main.nss_hal_common_init_done == false) {
/*
* Perform clock init common to all NSS cores
*/
struct clk *nss_tcm_src = NULL;
struct clk *nss_tcm_clk = NULL;
/*
* Attach debug interface to TLMM
*/
nss_write_32((uint32_t)nss_top_main.nss_fpb_base, NSS_REGS_FPB_CSR_CFG_OFFSET, 0x360);
/*
* NSS TCM CLOCK
*/
nss_tcm_src = clk_get(&nss_dev->dev, NSS_TCM_SRC_CLK);
if (IS_ERR(nss_tcm_src)) {
pr_err("nss-driver: cannot get clock: " NSS_TCM_SRC_CLK);
return -EFAULT;
}
clk_set_rate(nss_tcm_src, NSSTCM_FREQ);
clk_prepare(nss_tcm_src);
clk_enable(nss_tcm_src);
nss_tcm_clk = clk_get(&nss_dev->dev, NSS_TCM_CLK);
if (IS_ERR(nss_tcm_clk)) {
pr_err("nss-driver: cannot get clock: " NSS_TCM_CLK);
return -EFAULT;
}
clk_prepare(nss_tcm_clk);
clk_enable(nss_tcm_clk);
nss_top_main.nss_hal_common_init_done = true;
nss_info("nss_hal_common_reset Done.\n");
}
if (nss_dev->dev.of_node) {
/*
* Device Tree based init
*/
np = of_node_get(nss_dev->dev.of_node);
npd = nss_drv_of_get_pdata(np, nss_dev);
of_node_put(np);
if (!npd) {
return -EFAULT;
}
nss_ctx = &nss_top->nss[npd->id];
nss_ctx->id = npd->id;
nss_dev->id = nss_ctx->id;
} else {
/*
* Platform Device based init
*/
npd = (struct nss_platform_data *) nss_dev->dev.platform_data;
nss_ctx = &nss_top->nss[nss_dev->id];
nss_ctx->id = nss_dev->id;
}
#else
npd = (struct nss_platform_data *) nss_dev->dev.platform_data;
nss_ctx = &nss_top->nss[nss_dev->id];
nss_ctx->id = nss_dev->id;
#endif
nss_ctx->nss_top = nss_top;
nss_info("%p: NSS_DEV_ID %s \n", nss_ctx, dev_name(&nss_dev->dev));
/*
* F/W load from NSS Driver
*/
if (nss_ctx->id == 0) {
rc = request_firmware(&nss_fw, NETAP0_IMAGE, &(nss_dev->dev));
} else if (nss_ctx->id == 1) {
rc = request_firmware(&nss_fw, NETAP1_IMAGE, &(nss_dev->dev));
} else {
nss_warning("%p: Invalid nss dev: %d \n", nss_ctx, nss_dev->id);
}
/*
* Check if the file read is successful
*/
if (rc) {
nss_warning("%p: request_firmware failed with err code: %d", nss_ctx, rc);
err = rc;
goto err_init_0;
}
if (nss_fw->size < MIN_IMG_SIZE) {
nss_warning("%p: nss firmware is truncated, size:%d", nss_ctx, nss_fw->size);
}
load_mem = ioremap_nocache(npd->load_addr, nss_fw->size);
if (load_mem == NULL) {
nss_warning("%p: ioremap_nocache failed: %x", nss_ctx, npd->load_addr);
release_firmware(nss_fw);
goto err_init_0;
}
printk("nss_driver - fw of size %u bytes copied to load addr: %x, nss_id : %d\n", nss_fw->size, npd->load_addr, nss_dev->id);
memcpy_toio(load_mem, nss_fw->data, nss_fw->size);
release_firmware(nss_fw);
iounmap(load_mem);
/*
* Both NSS cores controlled by same regulator, Hook only Once
*/
if (!nss_ctx->id) {
nss_core0_clk = clk_get(&nss_dev->dev, "nss_core_clk");
if (IS_ERR(nss_core0_clk)) {
err = PTR_ERR(nss_core0_clk);
nss_info("%p: Regulator %s get failed, err=%d\n", nss_ctx, dev_name(&nss_dev->dev), err);
return err;
}
clk_set_rate(nss_core0_clk, NSS_FREQ_550);
clk_prepare(nss_core0_clk);
clk_enable(nss_core0_clk);
#if (NSS_PM_SUPPORT == 1)
/*
* Check if turbo is supported
*/
if (npd->turbo_frequency) {
/*
* Turbo is supported
*/
printk("nss_driver - Turbo Support %d\n", npd->turbo_frequency);
nss_runtime_samples.freq_scale_sup_max = NSS_MAX_CPU_SCALES;
nss_pm_set_turbo();
} else {
printk("nss_driver - Turbo No Support %d\n", npd->turbo_frequency);
nss_runtime_samples.freq_scale_sup_max = NSS_MAX_CPU_SCALES - 1;
}
#else
printk("nss_driver - Turbo Not Supported\n");
#endif
}
/*
* Get load address of NSS firmware
*/
nss_info("%p: Setting NSS%d Firmware load address to %x\n", nss_ctx, nss_ctx->id, npd->load_addr);
nss_top->nss[nss_ctx->id].load = npd->load_addr;
/*
* Get virtual and physical memory addresses for nss logical/hardware address maps
*/
/*
* Virtual address of CSM space
*/
nss_ctx->nmap = npd->nmap;
nss_assert(nss_ctx->nmap);
/*
* Physical address of CSM space
*/
nss_ctx->nphys = npd->nphys;
nss_assert(nss_ctx->nphys);
/*
* Virtual address of logical registers space
*/
nss_ctx->vmap = npd->vmap;
nss_assert(nss_ctx->vmap);
/*
* Physical address of logical registers space
*/
nss_ctx->vphys = npd->vphys;
nss_assert(nss_ctx->vphys);
nss_info("%d:ctx=%p, vphys=%x, vmap=%x, nphys=%x, nmap=%x",
nss_ctx->id, nss_ctx, nss_ctx->vphys, nss_ctx->vmap, nss_ctx->nphys, nss_ctx->nmap);
/*
* Register netdevice handlers
*/
nss_ctx->int_ctx[0].ndev = alloc_netdev(sizeof(struct netdev_priv_instance),
"qca-nss-dev%d", nss_dummy_netdev_setup);
if (nss_ctx->int_ctx[0].ndev == NULL) {
nss_warning("%p: Could not allocate net_device #0", nss_ctx);
err = -ENOMEM;
goto err_init_0;
}
nss_ctx->int_ctx[0].ndev->netdev_ops = &nss_netdev_ops;
nss_ctx->int_ctx[0].ndev->ethtool_ops = &nss_ethtool_ops;
err = register_netdev(nss_ctx->int_ctx[0].ndev);
if (err) {
nss_warning("%p: Could not register net_device #0", nss_ctx);
goto err_init_1;
}
/*
* request for IRQs
*
* WARNING: CPU affinities should be set using OS supported methods
*/
nss_ctx->int_ctx[0].nss_ctx = nss_ctx;
nss_ctx->int_ctx[0].shift_factor = 0;
nss_ctx->int_ctx[0].irq = npd->irq[0];
err = request_irq(npd->irq[0], nss_handle_irq, IRQF_DISABLED, "nss", &nss_ctx->int_ctx[0]);
if (err) {
nss_warning("%d: IRQ0 request failed", nss_dev->id);
goto err_init_2;
}
/*
* Register NAPI for NSS core interrupt #0
*/
ndev_priv = netdev_priv(nss_ctx->int_ctx[0].ndev);
ndev_priv->int_ctx = &nss_ctx->int_ctx[0];
netif_napi_add(nss_ctx->int_ctx[0].ndev, &nss_ctx->int_ctx[0].napi, nss_core_handle_napi, 64);
napi_enable(&nss_ctx->int_ctx[0].napi);
nss_ctx->int_ctx[0].napi_active = true;
/*
* Check if second interrupt is supported on this nss core
*/
if (npd->num_irq > 1) {
nss_info("%d: This NSS core supports two interrupts", nss_dev->id);
/*
* Register netdevice handlers
*/
nss_ctx->int_ctx[1].ndev = alloc_netdev(sizeof(struct netdev_priv_instance),
"qca-nss-dev%d", nss_dummy_netdev_setup);
if (nss_ctx->int_ctx[1].ndev == NULL) {
nss_warning("%p: Could not allocate net_device #1", nss_ctx);
err = -ENOMEM;
goto err_init_3;
}
nss_ctx->int_ctx[1].ndev->netdev_ops = &nss_netdev_ops;
nss_ctx->int_ctx[1].ndev->ethtool_ops = &nss_ethtool_ops;
err = register_netdev(nss_ctx->int_ctx[1].ndev);
if (err) {
nss_warning("%p: Could not register net_device #1", nss_ctx);
goto err_init_4;
}
nss_ctx->int_ctx[1].nss_ctx = nss_ctx;
nss_ctx->int_ctx[1].shift_factor = 15;
nss_ctx->int_ctx[1].irq = npd->irq[1];
err = request_irq(npd->irq[1], nss_handle_irq, IRQF_DISABLED, "nss", &nss_ctx->int_ctx[1]);
if (err) {
nss_warning("%d: IRQ1 request failed for nss", nss_dev->id);
goto err_init_5;
}
/*
* Register NAPI for NSS core interrupt #1
*/
ndev_priv = netdev_priv(nss_ctx->int_ctx[1].ndev);
ndev_priv->int_ctx = &nss_ctx->int_ctx[1];
netif_napi_add(nss_ctx->int_ctx[1].ndev, &nss_ctx->int_ctx[1].napi, nss_core_handle_napi, 64);
napi_enable(&nss_ctx->int_ctx[1].napi);
nss_ctx->int_ctx[1].napi_active = true;
}
spin_lock_bh(&(nss_top->lock));
/*
* Check functionalities are supported by this NSS core
*/
if (npd->shaping_enabled == NSS_FEATURE_ENABLED) {
nss_top->shaping_handler_id = nss_dev->id;
printk(KERN_INFO "%p: NSS Shaping is enabled, handler id: %u\n", __func__, nss_top->shaping_handler_id);
}
if (npd->ipv4_enabled == NSS_FEATURE_ENABLED) {
nss_top->ipv4_handler_id = nss_dev->id;
nss_ipv4_register_handler();
nss_pppoe_register_handler();
nss_eth_rx_register_handler();
nss_n2h_register_handler();
nss_virt_if_register_handler();
nss_lag_register_handler();
nss_dynamic_interface_register_handler();
nss_top->capwap_handler_id = nss_dev->id;
nss_capwap_init();
for (i = 0; i < NSS_MAX_VIRTUAL_INTERFACES; i++) {
nss_top->virt_if_handler_id[i] = nss_dev->id;
}
nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_802_3_REDIR] = nss_dev->id;
}
if (npd->ipv4_reasm_enabled == NSS_FEATURE_ENABLED) {
nss_top->ipv4_reasm_handler_id = nss_dev->id;
nss_ipv4_reasm_register_handler();
}
if (npd->ipv6_enabled == NSS_FEATURE_ENABLED) {
nss_top->ipv6_handler_id = nss_dev->id;
nss_ipv6_register_handler();
}
if (npd->crypto_enabled == NSS_FEATURE_ENABLED) {
nss_top->crypto_handler_id = nss_dev->id;
nss_crypto_register_handler();
}
if (npd->ipsec_enabled == NSS_FEATURE_ENABLED) {
nss_top->ipsec_handler_id = nss_dev->id;
nss_ipsec_register_handler();
}
if (npd->wlan_enabled == NSS_FEATURE_ENABLED) {
nss_top->wlan_handler_id = nss_dev->id;
}
if (npd->tun6rd_enabled == NSS_FEATURE_ENABLED) {
nss_top->tun6rd_handler_id = nss_dev->id;
}
if (npd->tunipip6_enabled == NSS_FEATURE_ENABLED) {
nss_top->tunipip6_handler_id = nss_dev->id;
nss_tunipip6_register_handler();
}
if (npd->gre_redir_enabled == NSS_FEATURE_ENABLED) {
nss_top->gre_redir_handler_id = nss_dev->id;
nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_GRE_REDIR] = nss_dev->id;
nss_gre_redir_register_handler();
nss_sjack_register_handler();
}
/*
* Mark data plane enabled so when nss core init done we call register to nss-gmac
*/
for (i = 0 ; i < NSS_MAX_PHYSICAL_INTERFACES ; i ++) {
if (npd->gmac_enabled[i] == NSS_FEATURE_ENABLED) {
nss_data_plane_set_enabled(i);
}
}
#if (NSS_PM_SUPPORT == 1)
nss_freq_register_handler();
#endif
nss_lso_rx_register_handler();
nss_top->frequency_handler_id = nss_dev->id;
spin_unlock_bh(&(nss_top->lock));
/*
* Initialize decongestion callbacks to NULL
*/
for (i = 0; i< NSS_MAX_CLIENTS; i++) {
nss_ctx->queue_decongestion_callback[i] = 0;
nss_ctx->queue_decongestion_ctx[i] = 0;
}
spin_lock_init(&(nss_ctx->decongest_cb_lock));
nss_ctx->magic = NSS_CTX_MAGIC;
nss_info("%p: Reseting NSS core %d now", nss_ctx, nss_ctx->id);
/*
* Enable clocks and bring NSS core out of reset
*/
#if (NSS_DT_SUPPORT == 1)
/*
* Remove UBI32 reset clamp
*/
rstctl = devm_reset_control_get(&nss_dev->dev, "clkrst_clamp");
if (IS_ERR(rstctl)) {
nss_info("%p: Deassert UBI32 reset clamp failed", nss_ctx, nss_ctx->id);
err = -EFAULT;
goto err_init_5;
}
reset_control_deassert(rstctl);
mdelay(1);
reset_control_put(rstctl);
/*
* Remove UBI32 core clamp
*/
rstctl = devm_reset_control_get(&nss_dev->dev, "clamp");
if (IS_ERR(rstctl)) {
nss_info("%p: Deassert UBI32 core clamp failed", nss_ctx, nss_ctx->id);
err = -EFAULT;
goto err_init_5;
}
reset_control_deassert(rstctl);
mdelay(1);
reset_control_put(rstctl);
/*
* Remove UBI32 AHB reset
*/
rstctl = devm_reset_control_get(&nss_dev->dev, "ahb");
if (IS_ERR(rstctl)) {
nss_info("%p: Deassert AHB reset failed", nss_ctx, nss_ctx->id);
err = -EFAULT;
goto err_init_5;
}
reset_control_deassert(rstctl);
mdelay(1);
reset_control_put(rstctl);
/*
* Remove UBI32 AXI reset
*/
rstctl = devm_reset_control_get(&nss_dev->dev, "axi");
if (IS_ERR(rstctl)) {
nss_info("%p: Deassert AXI reset failed", nss_ctx, nss_ctx->id);
err = -EFAULT;
goto err_init_5;
}
reset_control_deassert(rstctl);
mdelay(1);
reset_control_put(rstctl);
nss_hal_core_reset(nss_ctx->nmap, nss_ctx->load);
#else
nss_hal_core_reset(nss_dev->id, nss_ctx->nmap, nss_ctx->load, nss_top->clk_src);
#endif
/*
* Enable interrupts for NSS core
*/
nss_hal_enable_interrupt(nss_ctx->nmap, nss_ctx->int_ctx[0].irq,
nss_ctx->int_ctx[0].shift_factor, NSS_HAL_SUPPORTED_INTERRUPTS);
if (npd->num_irq > 1) {
nss_hal_enable_interrupt(nss_ctx->nmap, nss_ctx->int_ctx[1].irq,
nss_ctx->int_ctx[1].shift_factor, NSS_HAL_SUPPORTED_INTERRUPTS);
}
/*
* Initialize max buffer size for NSS core
*/
nss_ctx->max_buf_size = NSS_NBUF_PAYLOAD_SIZE;
nss_info("%p: All resources initialized and nss core%d has been brought out of reset", nss_ctx, nss_dev->id);
goto err_init_0;
err_init_5:
unregister_netdev(nss_ctx->int_ctx[1].ndev);
err_init_4:
free_netdev(nss_ctx->int_ctx[1].ndev);
err_init_3:
free_irq(npd->irq[0], &nss_ctx->int_ctx[0]);
err_init_2:
unregister_netdev(nss_ctx->int_ctx[0].ndev);
err_init_1:
free_netdev(nss_ctx->int_ctx[0].ndev);
#if (NSS_DT_SUPPORT == 1)
if (nss_dev->dev.of_node) {
if (npd->nmap) {
iounmap((void *)npd->nmap);
}
if (npd->vmap) {
iounmap((void *)npd->vmap);
}
}
#endif
err_init_0:
#if (NSS_DT_SUPPORT == 1)
if (nss_dev->dev.of_node) {
devm_kfree(&nss_dev->dev, npd);
}
#endif
return err;
}
