int linux_read(int fd, void *buf, size_t count)
{
ssize_t ret;
if (count == 0)
return 0;
do {
ret = read(fd, buf, count);
if (ret == 0) {
printf("read on fd %d returned 0, device gone? - exiting\n", fd);
reset_cpu(0);
} else if (ret == -1) {
if (errno == EAGAIN)
return -errno;
else if (errno == EINTR)
continue;
else {
printf("read on fd %d returned -1, errno %d - exiting\n", fd, errno);
reset_cpu(0);
}
}
} while (ret <= 0);
return (int)ret;
}
void __efi_runtime EFIAPI efi_reset_system(
enum efi_reset_type reset_type,
efi_status_t reset_status,
unsigned long data_size, void *reset_data)
{
u32 val;
switch (reset_type) {
case EFI_RESET_COLD:
case EFI_RESET_WARM:
case EFI_RESET_PLATFORM_SPECIFIC:
reset_cpu(0);
break;
case EFI_RESET_SHUTDOWN:
/*
* We set the watchdog hard reset bit here to distinguish this reset
* from the normal (full) reset. bootcode.bin will not reboot after a
* hard reset.
*/
val = readl(&wdog_regs->rsts);
val |= BCM2835_WDOG_PASSWORD;
val |= BCM2835_WDOG_RSTS_RASPBERRYPI_HALT;
writel(val, &wdog_regs->rsts);
reset_cpu(0);
break;
}
while (1) { }
}
void ml2f_reboot(void)
{
reset_cpu();
/* sending an reset signal to EC(embedded controller) */
ec_write(REG_RESET, BIT_RESET_ON);
}
envm_write_and_reset(ulong dst, ulong src, ulong size, int do_reset)
{
int ret = 0;
/*
* Copy the buffer to the destination.
*/
if (envm_write((uint) dst, (void *) src, (uint) size) != size) {
ret = -1;
goto Done;
}
/*
* If the user needs a reset, do the reset
*/
if (do_reset) {
/*
* Cortex-M3 core reset.
*/
reset_cpu(0);
/*
* Should never be here.
*/
}
Done:
return ret;
}
static int do_bootm_linux(struct image_data *data)
{
void (*kernel)(void *, void *, unsigned long,
unsigned long, unsigned long);
if (!data->os_res)
return -EINVAL;
data->oftree = of_get_fixed_tree(data->of_root_node);
if (!data->oftree) {
pr_err("bootm: No devicetree given.\n");
return -EINVAL;
}
fdt_add_reserve_map(data->oftree);
kernel = (void *)(data->os_address + data->os_entry);
/*
* Linux Kernel Parameters (passing device tree):
* r3: ptr to OF flat tree, followed by the board info data
* r4: physical pointer to the kernel itself
* r5: NULL
* r6: NULL
* r7: NULL
*/
kernel(data->oftree, kernel, 0, 0, 0);
reset_cpu(0);
/* not reached */
return -1;
}
/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
int sunxi_board_run_fel(void)
{
#if defined(CONFIG_SUN6I) || defined(CONFIG_ARCH_SUN8IW3P1)|| defined(CONFIG_ARCH_SUN8IW5P1) || defined(CONFIG_ARCH_SUN7I)|| defined(CONFIG_ARCH_SUN8IW8P1)
*((volatile unsigned int *)(SUNXI_RUN_EFEX_ADDR)) = SUNXI_RUN_EFEX_FLAG;
#elif defined(CONFIG_ARCH_SUN9IW1P1) || defined(CONFIG_ARCH_SUN8IW7P1) || defined(CONFIG_ARCH_SUN8IW6P1)
sunxi_set_fel_flag();
#endif
printf("set next system status\n");
axp_set_next_poweron_status(PMU_PRE_SYS_MODE);
board_display_set_exit_mode(0);
#ifdef CONFIG_SUNXI_DISPLAY
drv_disp_exit();
#endif
printf("sunxi_board_close_source\n");
sunxi_board_close_source();
sunxi_flush_allcaches();
#if defined(CONFIG_ARCH_SUN5I)
printf("jump to fel_base\n");
jump_to(FEL_BASE);
#else
printf("reset cpu\n");
reset_cpu(0);
#endif
return 0;
}
usbMsgLen_t usbFunctionSetup(uint8_t data[8])
{
struct usbRequest *rq = (void *)data;
static union {
uint32_t l;
uint8_t b[4];
} temp;
switch (rq->bRequest) {
case CUSTOM_RQ_GET_TIME:
temp.l = time;
usbMsgPtr = (uint8_t *)&temp;
return sizeof(temp);
case CUSTOM_RQ_SET_TIME:
temp.b[0] = rq->wValue.bytes[0];
temp.b[1] = rq->wValue.bytes[1];
temp.b[2] = rq->wIndex.bytes[0];
temp.b[3] = rq->wIndex.bytes[1];
time = temp.l;
return 0;
case CUSTOM_RQ_RESET:
reset_cpu();
break;
}
return 0;
}
static int do_bootm_barebox(struct image_data *data)
{
void *barebox;
barebox = read_file(data->os_file, NULL);
if (!barebox)
return -EINVAL;
if (IS_ENABLED(CONFIG_OFTREE) && data->of_root_node) {
data->oftree = of_get_fixed_tree(data->of_root_node);
fdt_add_reserve_map(data->oftree);
of_print_cmdline(data->of_root_node);
if (bootm_verbose(data) > 1)
of_print_nodes(data->of_root_node, 0);
}
if (bootm_verbose(data)) {
printf("\nStarting barebox at 0x%p", barebox);
if (data->oftree)
printf(", oftree at 0x%p", data->oftree);
printf("...\n");
}
start_linux(barebox, 0, 0, 0, data->oftree);
reset_cpu(0);
}
void ddr3_check_ecc_int(u32 base)
{
char *env;
int ecc_test = 0;
u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
env = getenv("ecc_test");
if (env)
ecc_test = simple_strtol(env, NULL, 0);
if (value & KS2_DDR3_WR_ECC_ERR_SYS)
puts("DDR3 ECC write error interrupted\n");
if (value & KS2_DDR3_2B_ECC_ERR_SYS) {
puts("DDR3 ECC 2-bit error interrupted\n");
if (!ecc_test) {
puts("Reseting the device ...\n");
reset_cpu(0);
}
}
value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
if (value) {
printf("1-bit ECC err count: 0x%x\n", value);
value = __raw_readl(base +
KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET);
printf("1-bit ECC err address log: 0x%x\n", value);
}
}
/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
int sunxi_board_run_fel_eraly(void)
{
#if defined(CONFIG_SUN6I) || defined(CONFIG_ARCH_SUN8IW3P1) || defined(CONFIG_ARCH_SUN8IW5P1)|| defined(CONFIG_ARCH_SUN7I)||defined(CONFIG_ARCH_SUN8IW8P1)
*((volatile unsigned int *)(SUNXI_RUN_EFEX_ADDR)) = SUNXI_RUN_EFEX_FLAG;
#elif defined(CONFIG_ARCH_SUN9IW1P1) || defined(CONFIG_ARCH_SUN8IW7P1) || defined(CONFIG_ARCH_SUN8IW6P1)
sunxi_set_fel_flag();
#endif
printf("set next system status\n");
axp_set_next_poweron_status(PMU_PRE_SYS_MODE);
timer_exit();
sunxi_key_exit();
#ifdef CONFIG_SUN6I
p2wi_exit();
#endif
sunxi_dma_exit();
#if defined(CONFIG_ARCH_SUN5I)
printf("jump to fel_base\n");
jump_to(FEL_BASE);
#else
printf("reset cpu\n");
//#if defined(CONFIG_ARCH_SUN9IW1P1)
// *( volatile unsigned int *)(0x008000e0) = 0x16aa0000;
//#endif
reset_cpu(0);
#endif
return 0;
}
static int ddr_addrtrain(void)
{
ddrtr_t entry;
struct ddrtr_result_t *result;
struct ddrtr_param_t param;
param.cmd = DDRTR_PARAM_ADDRTRAIN;
entry = (ddrtr_t)get_ddrtr_entry();
if (!entry)
return -1;
printf("## DDR address training entry: 0x%08X, ", (unsigned int)entry);
asm("mcr p15, 0, r0, c7, c5, 0");
asm("mcr p15, 0, r0, c7, c10, 4");
result = entry(¶m);
if (!result) {
printf("## DDR address training fail, reset system.\n");
reset_cpu(0);
return 0;
}
memcpy((void *)&ddrtr_result, result, sizeof(ddrtr_result));
printf("## DDR address training terminated.\n");
ddr_training_result((unsigned int)(&(ddrtr_result.data)));
printf("\nDDR address training Registers and Value:\n");
printf(dump_ddrtr_result(result, '\n'));
return 0;
}
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
disable_interrupts ();
reset_cpu (0);
/*NOTREACHED*/
return (0);
}
static int do_tegrarcm(int argc, char *argv[])
{
writel(2, pmc_base + PMC_SCRATCH(0));
reset_cpu(0);
return 0;
}
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
extern void reset_cpu (ulong addr);
disable_interrupts ();
reset_cpu (0);
/*NOTREACHED*/
return (0);
}
int main(int argc,char *argv[]){
int exitcode = 0;
t_state state, *s=&state;
/* Parse command line and pass any relevant arguments to CPU record */
parse_cmd_line(argc,argv, &cmd_line_args);
fprintf(stderr,"ION (MIPS32 clone) core emulator (" __DATE__ ")\n\n");
if(!init_cpu(s, &cmd_line_args)){
fprintf(stderr,"Trouble allocating memory, quitting!\n");
exit(71);
};
/* Read binary object files into memory*/
if(!read_binary_files(s, &cmd_line_args)){
exit(66);
}
fprintf(stderr,"\n\n");
/* Open the CPU console output file if not stdout. */
if (cmd_line_args.conout_filename!=NULL) {
cpuconout = fopen(cmd_line_args.conout_filename, "w");
if (cpuconout==NULL){
fprintf(stderr,"Trouble opening console log file '%s', quitting.\n", cmd_line_args.conout_filename);
exitcode = 2;
goto main_quit;
}
}
else {
cpuconout = stdout;
}
init_trace_buffer(s, &cmd_line_args);
/* NOTE: Original mlite supported loading little-endian code, which this
program doesn't. The endianess-conversion code has been removed.
*/
/* Simulate a CPU reset */
reset_cpu(s);
/* Simulate the work of the uClinux bootloader */
if(cmd_line_args.memory_map == MAP_UCLINUX){
/* FIXME this 'bootloader' is a stub, flesh it out */
s->pc = 0x80002400;
}
/* Enter debug command interface; will only exit clean with user command */
do_debug(s, cmd_line_args.no_prompt);
main_quit:
/* Close and deallocate everything and quit */
close_trace_buffer(s);
free_cpu(s);
if (cmd_line_args.conout_filename!=NULL && cpuconout!=NULL) fclose(cpuconout);
exit(0);
}
void blackfin_irq_panic(int reason, struct pt_regs *regs)
{
printf("\n\nException: IRQ 0x%x entered\n", reason);
dump_regs(regs);
printf("Unhandled IRQ or exceptions!\n");
printf("Please reset the board \n");
reset_cpu(0);
}
void auto_sdfuse()
{
char cmd[16];
sprintf(cmd, "fdisk -c %d", BOOT_MMC);
run_command(cmd, 0);
run_command("sdfuse flashall", 0);
reset_cpu (0);
while(1);
}
static void goto_wakeup(void)
{
volatile U32 *pData, *pBase;
U32 size, sum, val=0, xor=0;
int i=0;
pBase = (volatile U32*)(SLEEP_PHY_BASE);
pData = (volatile U32*)(SLEEP_PHY_BASE + 0x8);
size = *(U32*)(SLEEP_PHY_BASE + 0x4);
sum = *(U32*)pBase;
/*
* Set alive power gating, NX_ALIVE_SetWriteEnable(CTRUE)
*/
WriteIODW((volatile U32*)REG_PWRGATEREG, (REG_PWRGATEREG | (0x1)));
/*
* Check scratch register, NX_ALIVE_GetScratchReg()
*/
if (CFG_PWR_SLEEP_SIGNATURE == *(volatile U32*)(REG_SCRATCHREADREG))
{
printf("%s: wakup mode\n", __func__);
/* Check size value */
if (size <= 0 || size >= 0x100) {
*pBase = 0x12345678;
printf("%s check size error(%d)\n", __func__, size);
return;
}
printf("%s: size(%d)\n", __func__, size);
/* Verify checksum value */
for (i = 0; i<size; i++, pData++) {
xor = (*pData ^ 0xAA);
val ^= xor;
}
/* if memory corrupted, goto boot sequency. */
if (sum != val) {
*pBase = 0x87654321;
return;
}
asm_cpu_wakeup();
/* Fail wake up, so reset */
serial_init();
serial_puts("Fail, u-boot wakeup, reset cpu ...\n");
reset_cpu(0);
}
/* Cold boot */
*pBase = 0x56781234;
}
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
printf ("resetting ...\n");
udelay (50000); /* wait 50 ms */
disable_interrupts ();
reset_cpu (0);
/*NOTREACHED*/
return (0);
}
void __noreturn hang (void)
{
puts ("### ERROR ### Please RESET the board ###\n");
puts ("Press \'r\' key to reset cpu\n");
for (;;){
int ch;
ch = GETC_LL();
PUTC_LL(ch);
if(ch == 'r') reset_cpu(0);
}
}
static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
puts("Entering RCM...\n");
udelay(50000);
tegra_pmc_writel(2, PMC_SCRATCH0);
disable_interrupts();
reset_cpu(0);
return 0;
}
int sunxi_board_run_fel_eraly(void)
{
sunxi_set_fel_flag();
printf("set next system status\n");
axp_set_next_poweron_status(PMU_PRE_SYS_MODE);
timer_exit();
sunxi_key_exit();
printf("reset cpu\n");
reset_cpu(0);
return 0;
}
/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
int sunxi_board_run_fel(void)
{
#if defined(CONFIG_SUN6I) || defined(CONFIG_ARCH_SUN8IW3P1)|| defined(CONFIG_ARCH_SUN8IW5P1) || defined(CONFIG_ARCH_SUN7I)
*((volatile unsigned int *)(SUNXI_RUN_EFEX_ADDR)) = SUNXI_RUN_EFEX_FLAG;
#elif defined(CONFIG_ARCH_SUN9IW1P1)
volatile unsigned int *rtc_addr = (volatile unsigned int *)(0x08001400 + 0x1f0);
do
{
*rtc_addr = (1<<16) | (SUNXI_RUN_EFEX_FLAG<<8);
*rtc_addr = (1<<31) | (1<<16) | (SUNXI_RUN_EFEX_FLAG<<8);
__usdelay(10);
*rtc_addr = (1<<16) | (SUNXI_RUN_EFEX_FLAG<<8);
}
while((*rtc_addr & 0xff) != SUNXI_RUN_EFEX_FLAG);
#elif defined(CONFIG_ARCH_SUN8IW6P1)
volatile unsigned int *rtc_addr = (volatile unsigned int *)(0x01f01400 + 0x1f0);
do
{
*rtc_addr = (1<<16) | (SUNXI_RUN_EFEX_FLAG<<8);
*rtc_addr = (1<<31) | (1<<16) | (SUNXI_RUN_EFEX_FLAG<<8);
__usdelay(10);
*rtc_addr = (1<<16) | (SUNXI_RUN_EFEX_FLAG<<8);
}
while((*rtc_addr & 0xff) != SUNXI_RUN_EFEX_FLAG);
#endif
printf("set next system status\n");
axp_set_next_poweron_status(PMU_PRE_SYS_MODE);
board_display_set_exit_mode(0);
#ifdef CONFIG_SUNXI_DISPLAY
drv_disp_exit();
#endif
printf("sunxi_board_close_source\n");
sunxi_board_close_source();
sunxi_flush_allcaches();
#if defined(CONFIG_ARCH_SUN5I)
printf("jump to fel_base\n");
jump_to(FEL_BASE);
#else
printf("reset cpu\n");
reset_cpu(0);
#endif
return 0;
}
static int do_bootm_barebox(struct image_data *data)
{
void (*barebox)(void);
barebox = read_file(data->os_file, NULL);
if (!barebox)
return -EINVAL;
shutdown_barebox();
barebox();
reset_cpu(0);
}
static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
puts("Entering RCM...\n");
udelay(50000);
pmc->pmc_scratch0 = 2;
disable_interrupts();
reset_cpu(0);
return 0;
}
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned int i;
#if defined(MV_INC_BOARD_DDIM)
unsigned int dramTotalSize=0;
#endif
MV_32 memBase;
#if defined(MV_INC_BOARD_DDIM)
/* Call dramInit */
if (0 == (dramTotalSize = initdram(0)))
{
printf("DRAM Initialization Failed\n");
reset_cpu();
return (1);
}
#endif
//mvIntrfaceParamPrint();
for(i = 0; i< MV_DRAM_MAX_CS; i++)
{
MV_CPU_DEC_WIN addrDecWin;
if((mvCpuIfTargetWinGet(SDRAM_CS0 + i, &addrDecWin) == MV_OK) &&
(addrDecWin.enable == MV_TRUE)){
memBase = addrDecWin.addrWin.baseLow;
gd->bd->bi_dram[i].start = memBase;
gd->bd->bi_dram[i].size = addrDecWin.addrWin.size;
}
//dramTotalSize += gd->bd->bi_dram[i].size;
// if (gd->bd->bi_dram[i].size)
// {
//printf("DRAM CS[%d] base 0x%08x ",i, gd->bd->bi_dram[i].start);
//mvSizePrint(gd->bd->bi_dram[i].size);
//printf("\n");
// }
}
// printf("DRAM Total ");
// mvSizePrint(dramTotalSize);
// mvIntrfaceWidthPrint();
// printf("\n");
#ifdef MV_INC_DRAM_MFG_TEST
mvDramMfgTrst();
#endif
return 0;
}
static int __do_bootm_linux(struct image_data *data, unsigned long free_mem, int swap)
{
unsigned long kernel;
unsigned long initrd_start = 0, initrd_size = 0, initrd_end = 0;
int ret;
kernel = data->os_res->start + data->os_entry;
initrd_start = data->initrd_address;
if (initrd_start == UIMAGE_INVALID_ADDRESS) {
initrd_start = PAGE_ALIGN(free_mem);
if (bootm_verbose(data)) {
printf("no initrd load address, defaulting to 0x%08lx\n",
initrd_start);
}
}
ret = bootm_load_initrd(data, initrd_start);
if (ret)
return ret;
if (data->initrd_res) {
initrd_start = data->initrd_res->start;
initrd_end = data->initrd_res->end;
initrd_size = resource_size(data->initrd_res);
free_mem = PAGE_ALIGN(initrd_end);
}
ret = bootm_load_devicetree(data, free_mem);
if (ret)
return ret;
if (bootm_verbose(data)) {
printf("\nStarting kernel at 0x%08lx", kernel);
if (initrd_size)
printf(", initrd at 0x%08lx", initrd_start);
if (data->oftree)
printf(", oftree at 0x%p", data->oftree);
printf("...\n");
}
start_linux((void *)kernel, swap, initrd_start, initrd_size, data->oftree);
reset_cpu(0);
return -ERESTARTSYS;
}
/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
int sunxi_board_restart(int next_mode)
{
if(!next_mode)
{
next_mode = PMU_PRE_SYS_MODE;
}
printf("set next mode %d\n", next_mode);
axp_set_next_poweron_status(next_mode);
board_display_set_exit_mode(0);
drv_disp_exit();
sunxi_board_close_source();
reset_cpu(0);
return 0;
}
/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
int sunxi_board_run_fel_eraly(void)
{
#if defined(CONFIG_SUN6I) || defined(CONFIG_ARCH_SUN8IW3P1) || defined(CONFIG_ARCH_SUN8IW5P1)|| defined(CONFIG_ARCH_SUN7I)
*((volatile unsigned int *)(SUNXI_RUN_EFEX_ADDR)) = SUNXI_RUN_EFEX_FLAG;
#elif defined(CONFIG_ARCH_SUN9IW1P1)
volatile unsigned int *rtc_addr = (volatile unsigned int *)(0x08001400 + 0x1f0);
do
{
*rtc_addr = (1<<16) | (SUNXI_RUN_EFEX_FLAG<<8);
*rtc_addr = (1<<31) | (1<<16) | (SUNXI_RUN_EFEX_FLAG<<8);
__usdelay(10);
*rtc_addr = (1<<16) | (SUNXI_RUN_EFEX_FLAG<<8);
}
while((*rtc_addr & 0xff) != SUNXI_RUN_EFEX_FLAG);
#elif defined(CONFIG_ARCH_SUN8IW6P1)
volatile unsigned int *rtc_addr = (volatile unsigned int *)(0x01f01400 + 0x1f0);
do
{
*rtc_addr = (1<<16) | (SUNXI_RUN_EFEX_FLAG<<8);
*rtc_addr = (1<<31) | (1<<16) | (SUNXI_RUN_EFEX_FLAG<<8);
__usdelay(10);
*rtc_addr = (1<<16) | (SUNXI_RUN_EFEX_FLAG<<8);
}
while((*rtc_addr & 0xff) != SUNXI_RUN_EFEX_FLAG);
#endif
printf("set next system status\n");
axp_set_next_poweron_status(PMU_PRE_SYS_MODE);
timer_exit();
sunxi_key_exit();
#ifdef CONFIG_SUN6I
p2wi_exit();
#endif
sunxi_dma_exit();
#if defined(CONFIG_ARCH_SUN5I)
printf("jump to fel_base\n");
jump_to(FEL_BASE);
#else
printf("reset cpu\n");
#if defined(CONFIG_ARCH_SUN9IW1P1)
*( volatile unsigned int *)(0x008000e0) = 0x16aa0000;
#endif
reset_cpu(0);
#endif
return 0;
}
int sunxi_board_run_fel(void)
{
sunxi_set_fel_flag();
printf("set next system status\n");
axp_set_next_poweron_status(PMU_PRE_SYS_MODE);
#ifdef CONFIG_SUNXI_DISPLAY
board_display_set_exit_mode(0);
drv_disp_exit();
#endif
printf("sunxi_board_close_source\n");
sunxi_board_close_source();
sunxi_flush_allcaches();
printf("reset cpu\n");
reset_cpu(0);
return 0;
}
