static void sig_handler(int signum)
{
t_ios term;
t_wsize ws;
char str[2];
if (signum == SIGCONT || signum == SIGWINCH)
{
reset_val(&term, &ws, 1);
signal(SIGTSTP, &sig_handler);
}
else if (signum == SIGINT || signum == SIGTERM || signum == SIGQUIT)
leave_term();
else if (signum == SIGTSTP)
{
if (isatty(1))
{
reset_val(&term, &ws, 1);
str[0] = term.c_cc[VSUSP];
str[1] = '\0';
tputs(tgetstr("ve", NULL), 0, &ft_putterm);
tputs(tgetstr("te", NULL), 0, &ft_putterm);
ioctl(0, TIOCSTI, str);
signal(SIGTSTP, SIG_DFL);
}
}
}
Set_of_p<Vertex>
internal_artic_pts_ATTLC(const Graph& g, const Set_of_p<Vertex>& v1_pset) {
//parameter is the vertex set in this connected component being inspected
Set_of_p<Vertex> v_pset2;
int j = 0;
int* i = &j; //"id" in Sedgewick
int k = 0;
int* childcount = &k;
Vertex* root_v;
Set_of_piter<Vertex> vpset_iter(v1_pset);
root_v = vpset_iter.next(); //choose any v in the set as the root
if (root_v) {
Val_v_ticket vt = Vertex::get_val_v_ticket();
artic_sub(root_v, childcount, root_v, i, v_pset2, g, vt);
if ((*childcount) < 2)
v_pset2.remove(root_v);
reset_val(vt, (Set_of_p<Vertex>&)v1_pset);
Vertex::free_val_v_ticket(vt);
}
return(v_pset2);
}
void move_list(t_win *win, t_ios *term, int x, int y)
{
char *buf;
int select;
t_wsize ws;
int resize;
if (tcsetattr(0, TCSADRAIN, term) == -1)
leave_term();
buf = ft_memalloc(5);
win->stop = 0;
read(0, buf, 3);
resize = reset_val(term, &ws, 0);
if (resize != 0)
{
y = win->position / win->max_y;
x = win->position % win->max_y;
check_move(buf, &y, &x, win);
select = check_buf(buf, win, win->position, term);
get_position(win, select, &x, &y);
print_arg(&(win->arg), win, win->position, find_space(win->arg));
}
free(buf);
}
#define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \
.hold_shift = hs, .bypass_shift = bs }
#define asiu_gate_val(o, es) { .offset = o, .en_shift = es }
static void __init cygnus_armpll_init(struct device_node *node)
{
iproc_armpll_setup(node);
}
CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
static const struct iproc_pll_ctrl genpll = {
.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
IPROC_CLK_PLL_NEEDS_SW_CFG,
.aon = aon_val(0x0, 2, 1, 0),
.reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
.sw_ctrl = sw_ctrl_val(0x10, 31),
.ndiv_int = reg_val(0x10, 20, 10),
.ndiv_frac = reg_val(0x10, 0, 20),
.pdiv = reg_val(0x14, 0, 4),
.vco_ctrl = vco_ctrl_val(0x18, 0x1c),
.status = reg_val(0x28, 12, 1),
};
static const struct iproc_clk_ctrl genpll_clk[] = {
[BCM_CYGNUS_GENPLL_AXI21_CLK] = {
.channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
.flags = IPROC_CLK_AON,
.enable = enable_val(0x4, 6, 0, 12),
.mdiv = reg_val(0x20, 0, 8),
},
