static void qe_muram_init(void)
{
struct device_node *np;
const u32 *address;
u64 size;
unsigned int flags;
/* initialize the info header */
rh_init(&qe_muram_info, 1,
sizeof(qe_boot_muram_rh_block) /
sizeof(qe_boot_muram_rh_block[0]), qe_boot_muram_rh_block);
/* Attach the usable muram area */
/* XXX: This is a subset of the available muram. It
* varies with the processor and the microcode patches activated.
*/
np = of_find_compatible_node(NULL, NULL, "fsl,qe-muram-data");
if (!np) {
np = of_find_node_by_name(NULL, "data-only");
if (!np) {
WARN_ON(1);
return;
}
}
address = of_get_address(np, 0, &size, &flags);
WARN_ON(!address);
of_node_put(np);
if (address)
rh_attach_region(&qe_muram_info, *address, (int)size);
}
int cpm_muram_init(void)
{
struct device_node *np;
struct resource r;
u32 zero[OF_MAX_ADDR_CELLS] = {};
resource_size_t max = 0;
int i = 0;
int ret = 0;
if (muram_pbase)
return 0;
spin_lock_init(&cpm_muram_lock);
/* initialize the info header */
rh_init(&cpm_muram_info, 1,
sizeof(cpm_boot_muram_rh_block) /
sizeof(cpm_boot_muram_rh_block[0]),
cpm_boot_muram_rh_block);
np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data");
if (!np) {
/* try legacy bindings */
np = of_find_node_by_name(NULL, "data-only");
if (!np) {
printk(KERN_ERR "Cannot find CPM muram data node");
ret = -ENODEV;
goto out;
}
}
muram_pbase = of_translate_address(np, zero);
if (muram_pbase == (phys_addr_t)OF_BAD_ADDR) {
printk(KERN_ERR "Cannot translate zero through CPM muram node");
ret = -ENODEV;
goto out;
}
while (of_address_to_resource(np, i++, &r) == 0) {
if (r.end > max)
max = r.end;
rh_attach_region(&cpm_muram_info, r.start - muram_pbase,
resource_size(&r));
}
muram_vbase = ioremap(muram_pbase, max - muram_pbase + 1);
if (!muram_vbase) {
printk(KERN_ERR "Cannot map CPM muram");
ret = -ENOMEM;
}
out:
of_node_put(np);
return ret;
}
BOOL APIENTRY DllMain(HANDLE module, DWORD reason, LPVOID reserved)
{
switch (reason)
{
case DLL_PROCESS_ATTACH:
rh_init();
break;
case DLL_THREAD_ATTACH:
break;
case DLL_THREAD_DETACH:
break;
case DLL_PROCESS_DETACH:
rh_finalize();
break;
}
return TRUE;
}
static void cpm2_dpinit(void)
{
spin_lock_init(&cpm_dpmem_lock);
/* initialize the info header */
rh_init(&cpm_dpmem_info, 1,
sizeof(cpm_boot_dpmem_rh_block) /
sizeof(cpm_boot_dpmem_rh_block[0]),
cpm_boot_dpmem_rh_block);
/* Attach the usable dpmem area */
/* XXX: This is actually crap. CPM_DATAONLY_BASE and
* CPM_DATAONLY_SIZE is only a subset of the available dpram. It
* varies with the processor and the microcode patches activated.
* But the following should be at least safe.
*/
rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
}
void m8xx_cpm_dpinit(void)
{
cpm8xx_t *cp = &((immap_t *)IMAP_ADDR)->im_cpm;
spin_lock_init(&cpm_dpmem_lock);
/* Initialize the info header */
rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
sizeof(cpm_boot_dpmem_rh_block) /
sizeof(cpm_boot_dpmem_rh_block[0]),
cpm_boot_dpmem_rh_block);
/*
* Attach the usable dpmem area.
* XXX: This is actually crap. CPM_DATAONLY_BASE and
* CPM_DATAONLY_SIZE are a subset of the available dparm. It varies
* with the processor and the microcode patches applied / activated.
* But the following should be at least safe.
*/
rh_attach_region(&cpm_dpmem_info, (void *)CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
}
static void qe_muram_init(void)
{
struct device_node *np;
u32 address;
u64 size;
unsigned int flags;
/* initialize the info header */
rh_init(&qe_muram_info, 1,
sizeof(qe_boot_muram_rh_block) /
sizeof(qe_boot_muram_rh_block[0]), qe_boot_muram_rh_block);
/* Attach the usable muram area */
/* XXX: This is a subset of the available muram. It
* varies with the processor and the microcode patches activated.
*/
if ((np = of_find_node_by_name(NULL, "data-only")) != NULL) {
address = *of_get_address(np, 0, &size, &flags);
of_node_put(np);
rh_attach_region(&qe_muram_info, address, (int) size);
}
}
