void board_init_f(ulong dummy)
{
struct udevice *pinctrl;
struct udevice *dev;
struct rk3399_pmusgrf_regs *sgrf;
struct rk3399_grf_regs *grf;
int ret;
#define EARLY_UART
#ifdef EARLY_UART
/*
* Debug UART can be used from here if required:
*
* debug_uart_init();
* printch('a');
* printhex8(0x1234);
* printascii("string");
*/
debug_uart_init();
printascii("U-Boot SPL board init");
#endif
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
/*
* Disable DDR and SRAM security regions.
*
* As we are entered from the BootROM, the region from
* 0x0 through 0xfffff (i.e. the first MB of memory) will
* be protected. This will cause issues with the DW_MMC
* driver, which tries to DMA from/to the stack (likely)
* located in this range.
*/
sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
/* eMMC clock generator: disable the clock multipilier */
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
rk_clrreg(&grf->emmccore_con[11], 0x0ff);
secure_timer_init();
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
if (ret) {
debug("Pinctrl init failed: %d\n", ret);
return;
}
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("DRAM init failed: %d\n", ret);
return;
}
}
static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
const struct pll_div *div)
{
int pll_id = rk_pll_id(clk_id);
struct rk3288_pll *pll = &cru->pll[pll_id];
/* All PLLs have same VCO and output frequency range restrictions. */
uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
uint output_hz = vco_hz / div->no;
debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
(uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
(div->no == 1 || !(div->no % 2)));
/* enter reset */
rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
rk_clrsetreg(&pll->con0,
CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
udelay(10);
/* return from reset */
rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
return 0;
}
int board_early_init_f(void)
{
const uintptr_t GRF_SOC_CON0 = 0xff770244;
const uintptr_t GRF_SOC_CON2 = 0xff77024c;
struct udevice *dev;
int ret;
/*
* This init is done in SPL, but when chain-loading U-Boot SPL will
* have been skipped. Allow the clock driver to check if it needs
* setting up.
*/
ret = rockchip_get_clk(&dev);
if (ret) {
debug("CLK init failed: %d\n", ret);
return ret;
}
rk_setreg(GRF_SOC_CON2, 1 << 0);
/*
* Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is
* cleared
*/
rk_clrreg(GRF_SOC_CON0, 1 << 12);
return 0;
}
int arch_cpu_init(void)
{
/* We do some SoC one time setting here. */
/* Emmc clock generator: disable the clock multipilier */
rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
return 0;
}
int arch_cpu_init(void)
{
/* We do some SoC one time setting here. */
/* Emmc clock generator: disable the clock multipilier */
rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
printf("time %x, %x\n", readl(0xff8680a8), readl(0xff8680ac));
return 0;
}
int rk3288_reset_request(struct udevice *dev, enum reset_t type)
{
struct rk3288_cru *cru = rockchip_get_cru();
if (IS_ERR(cru))
return PTR_ERR(cru);
switch (type) {
case RESET_WARM:
rk_clrreg(&cru->cru_mode_con, 0xffff);
writel(0xeca8, &cru->cru_glb_srst_snd_value);
break;
case RESET_COLD:
rk_clrreg(&cru->cru_mode_con, 0xffff);
writel(0xfdb9, &cru->cru_glb_srst_fst_value);
break;
default:
return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
}
static int rockchip_reset_deassert(struct reset_ctl *reset_ctl)
{
struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
reset_ctl, reset_ctl->dev, reset_ctl->id,
priv->base + (bank * 4));
rk_clrreg(priv->base + (bank * 4), BIT(offset));
return 0;
}
void board_init_f(ulong dummy)
{
int ret;
ret = spl_early_init();
if (ret) {
printf("spl_early_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
/* Disable the ddr secure region setting to make it non-secure */
rk_clrreg(SGRF_DDR_CON0, 0x4000);
}
static void rk3288_detect_reset_reason(void)
{
struct rk3288_cru *cru = rockchip_get_cru();
const char *reason;
if (IS_ERR(cru))
return;
switch (cru->cru_glb_rst_st) {
case GLB_POR_RST:
reason = "POR";
break;
case FST_GLB_RST_ST:
case SND_GLB_RST_ST:
reason = "RST";
break;
case FST_GLB_TSADC_RST_ST:
case SND_GLB_TSADC_RST_ST:
reason = "THERMAL";
break;
case FST_GLB_WDT_RST_ST:
case SND_GLB_WDT_RST_ST:
reason = "WDOG";
break;
default:
reason = "unknown reset";
}
env_set("reset_reason", reason);
/*
* Clear cru_glb_rst_st, so we can determine the last reset cause
* for following resets.
*/
rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
}
