static void
store_register (struct regcache *regcache, int regno)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
int addr[MAX_REGISTER_SIZE];
int nr, isfloat;
/* Fetch the register's value from the register cache. */
regcache_raw_collect (regcache, regno, addr);
/* -1 can be a successful return value, so infer errors from errno. */
errno = 0;
nr = regmap (gdbarch, regno, &isfloat);
/* Floating-point registers. */
if (isfloat)
rs6000_ptrace32 (PT_WRITE_FPR, ptid_get_pid (inferior_ptid), addr, nr, 0);
/* Bogus register number. */
else if (nr < 0)
{
if (regno >= gdbarch_num_regs (gdbarch))
fprintf_unfiltered (gdb_stderr,
"gdb error: register no %d not implemented.\n",
regno);
}
/* Fixed-point registers. */
else
{
/* The PT_WRITE_GPR operation is rather odd. For 32-bit inferiors,
the register's value is passed by value, but for 64-bit inferiors,
the address of a buffer containing the value is passed. */
if (!ARCH64 ())
rs6000_ptrace32 (PT_WRITE_GPR, ptid_get_pid (inferior_ptid),
(int *) nr, *addr, 0);
else
{
/* PT_WRITE_GPR requires the buffer parameter to point to an 8-byte
area, even if the register is really only 32 bits. */
long long buf;
if (register_size (gdbarch, regno) == 8)
memcpy (&buf, addr, 8);
else
buf = *addr;
rs6000_ptrace64 (PT_WRITE_GPR, ptid_get_pid (inferior_ptid),
nr, 0, &buf);
}
}
if (errno)
{
perror (_("ptrace write"));
errno = 0;
}
}
static void
fetch_register (struct regcache *regcache, int regno)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
int addr[MAX_REGISTER_SIZE];
int nr, isfloat;
/* Retrieved values may be -1, so infer errors from errno. */
errno = 0;
nr = regmap (gdbarch, regno, &isfloat);
/* Floating-point registers. */
if (isfloat)
rs6000_ptrace32 (PT_READ_FPR, ptid_get_pid (inferior_ptid), addr, nr, 0);
/* Bogus register number. */
else if (nr < 0)
{
if (regno >= gdbarch_num_regs (gdbarch))
fprintf_unfiltered (gdb_stderr,
"gdb error: register no %d not implemented.\n",
regno);
return;
}
/* Fixed-point registers. */
else
{
if (!ARCH64 ())
*addr = rs6000_ptrace32 (PT_READ_GPR, ptid_get_pid (inferior_ptid),
(int *) nr, 0, 0);
else
{
/* PT_READ_GPR requires the buffer parameter to point to long long,
even if the register is really only 32 bits. */
long long buf;
rs6000_ptrace64 (PT_READ_GPR, ptid_get_pid (inferior_ptid),
nr, 0, &buf);
if (register_size (gdbarch, regno) == 8)
memcpy (addr, &buf, 8);
else
*addr = buf;
}
}
if (!errno)
regcache_raw_supply (regcache, regno, (char *) addr);
else
{
#if 0
/* FIXME: this happens 3 times at the start of each 64-bit program. */
perror (_("ptrace read"));
#endif
errno = 0;
}
}
static gdb_byte *
rs6000_ptrace_ldinfo (ptid_t ptid)
{
const int pid = ptid_get_pid (ptid);
int ldi_size = 1024;
gdb_byte *ldi = xmalloc (ldi_size);
int rc = -1;
while (1)
{
if (ARCH64 ())
rc = rs6000_ptrace64 (PT_LDINFO, pid, (unsigned long) ldi, ldi_size,
NULL);
else
rc = rs6000_ptrace32 (PT_LDINFO, pid, (int *) ldi, ldi_size, NULL);
if (rc != -1)
break; /* Success, we got the entire ld_info data. */
if (errno != ENOMEM)
perror_with_name (_("ptrace ldinfo"));
/* ldi is not big enough. Double it and try again. */
ldi_size *= 2;
ldi = xrealloc (ldi, ldi_size);
}
return ldi;
}
static gdb::byte_vector
rs6000_ptrace_ldinfo (ptid_t ptid)
{
const int pid = ptid.pid ();
gdb::byte_vector ldi (1024);
int rc = -1;
while (1)
{
if (ARCH64 ())
rc = rs6000_ptrace64 (PT_LDINFO, pid, (unsigned long) ldi.data (),
ldi.size (), NULL);
else
rc = rs6000_ptrace32 (PT_LDINFO, pid, (int *) ldi.data (),
ldi.size (), NULL);
if (rc != -1)
break; /* Success, we got the entire ld_info data. */
if (errno != ENOMEM)
perror_with_name (_("ptrace ldinfo"));
/* ldi is not big enough. Double it and try again. */
ldi.resize (ldi.size () * 2);
}
return ldi;
}
static int
read_word (CORE_ADDR from, int *to, int arch64)
{
/* Retrieved values may be -1, so infer errors from errno. */
errno = 0;
if (arch64)
*to = rs6000_ptrace64 (PT_READ_I, PIDGET (inferior_ptid), from, 0, NULL);
else
*to = rs6000_ptrace32 (PT_READ_I, PIDGET (inferior_ptid), (int *)(long) from,
0, NULL);
return !errno;
}
void
xcoff_relocate_symtab (unsigned int pid)
{
int load_segs = 64; /* number of load segments */
int rc;
LdInfo *ldi = NULL;
int arch64 = ARCH64 ();
int ldisize = arch64 ? sizeof (ldi->l64) : sizeof (ldi->l32);
int size;
do
{
size = load_segs * ldisize;
ldi = (void *) xrealloc (ldi, size);
#if 0
/* According to my humble theory, AIX has some timing problems and
when the user stack grows, kernel doesn't update stack info in time
and ptrace calls step on user stack. That is why we sleep here a
little, and give kernel to update its internals. */
usleep (36000);
#endif
if (arch64)
rc = rs6000_ptrace64 (PT_LDINFO, pid, (unsigned long) ldi, size, NULL);
else
rc = rs6000_ptrace32 (PT_LDINFO, pid, (int *) ldi, size, NULL);
if (rc == -1)
{
if (errno == ENOMEM)
load_segs *= 2;
else
perror_with_name ("ptrace ldinfo");
}
else
{
vmap_ldinfo (ldi);
vmap_exec (); /* relocate the exec and core sections as well. */
}
} while (rc == -1);
if (ldi)
xfree (ldi);
}
static void
exec_one_dummy_insn (struct regcache *regcache)
{
#define DUMMY_INSN_ADDR AIX_TEXT_SEGMENT_BASE+0x200
struct gdbarch *gdbarch = get_regcache_arch (regcache);
int ret, status, pid;
CORE_ADDR prev_pc;
void *bp;
/* We plant one dummy breakpoint into DUMMY_INSN_ADDR address. We
assume that this address will never be executed again by the real
code. */
bp = deprecated_insert_raw_breakpoint (gdbarch, NULL, DUMMY_INSN_ADDR);
/* You might think this could be done with a single ptrace call, and
you'd be correct for just about every platform I've ever worked
on. However, rs6000-ibm-aix4.1.3 seems to have screwed this up --
the inferior never hits the breakpoint (it's also worth noting
powerpc-ibm-aix4.1.3 works correctly). */
prev_pc = regcache_read_pc (regcache);
regcache_write_pc (regcache, DUMMY_INSN_ADDR);
if (ARCH64 ())
ret = rs6000_ptrace64 (PT_CONTINUE, ptid_get_pid (inferior_ptid),
1, 0, NULL);
else
ret = rs6000_ptrace32 (PT_CONTINUE, ptid_get_pid (inferior_ptid),
(int *) 1, 0, NULL);
if (ret != 0)
perror (_("pt_continue"));
do
{
pid = waitpid (ptid_get_pid (inferior_ptid), &status, 0);
}
while (pid != ptid_get_pid (inferior_ptid));
regcache_write_pc (regcache, prev_pc);
deprecated_remove_raw_breakpoint (gdbarch, bp);
}
static void
exec_one_dummy_insn (struct gdbarch *gdbarch)
{
#define DUMMY_INSN_ADDR gdbarch_tdep (gdbarch)->text_segment_base+0x200
int ret, status, pid;
CORE_ADDR prev_pc;
void *bp;
/* We plant one dummy breakpoint into DUMMY_INSN_ADDR address. We
assume that this address will never be executed again by the real
code. */
bp = deprecated_insert_raw_breakpoint (DUMMY_INSN_ADDR);
/* You might think this could be done with a single ptrace call, and
you'd be correct for just about every platform I've ever worked
on. However, rs6000-ibm-aix4.1.3 seems to have screwed this up --
the inferior never hits the breakpoint (it's also worth noting
powerpc-ibm-aix4.1.3 works correctly). */
prev_pc = read_pc ();
write_pc (DUMMY_INSN_ADDR);
if (ARCH64 ())
ret = rs6000_ptrace64 (PT_CONTINUE, PIDGET (inferior_ptid), 1, 0, NULL);
else
ret = rs6000_ptrace32 (PT_CONTINUE, PIDGET (inferior_ptid), (int *)1, 0, NULL);
if (ret != 0)
perror ("pt_continue");
do
{
pid = wait (&status);
}
while (pid != PIDGET (inferior_ptid));
write_pc (prev_pc);
deprecated_remove_raw_breakpoint (bp);
}
static void
exec_one_dummy_insn (void)
{
#define DUMMY_INSN_ADDR (TEXT_SEGMENT_BASE)+0x200
char shadow_contents[BREAKPOINT_MAX]; /* Stash old bkpt addr contents */
int ret, status, pid;
CORE_ADDR prev_pc;
/* We plant one dummy breakpoint into DUMMY_INSN_ADDR address. We
assume that this address will never be executed again by the real
code. */
target_insert_breakpoint (DUMMY_INSN_ADDR, shadow_contents);
/* You might think this could be done with a single ptrace call, and
you'd be correct for just about every platform I've ever worked
on. However, rs6000-ibm-aix4.1.3 seems to have screwed this up --
the inferior never hits the breakpoint (it's also worth noting
powerpc-ibm-aix4.1.3 works correctly). */
prev_pc = read_pc ();
write_pc (DUMMY_INSN_ADDR);
if (ARCH64 ())
ret = rs6000_ptrace64 (PT_CONTINUE, PIDGET (inferior_ptid), 1, 0, NULL);
else
ret = rs6000_ptrace32 (PT_CONTINUE, PIDGET (inferior_ptid), (int *)1, 0, NULL);
if (ret != 0)
perror ("pt_continue");
do
{
pid = wait (&status);
}
while (pid != PIDGET (inferior_ptid));
write_pc (prev_pc);
target_remove_breakpoint (DUMMY_INSN_ADDR, shadow_contents);
}
static enum target_xfer_status
rs6000_xfer_partial (struct target_ops *ops, enum target_object object,
const char *annex, gdb_byte *readbuf,
const gdb_byte *writebuf,
ULONGEST offset, ULONGEST len, ULONGEST *xfered_len)
{
pid_t pid = ptid_get_pid (inferior_ptid);
int arch64 = ARCH64 ();
switch (object)
{
case TARGET_OBJECT_LIBRARIES_AIX:
return rs6000_xfer_shared_libraries (ops, object, annex,
readbuf, writebuf,
offset, len, xfered_len);
case TARGET_OBJECT_MEMORY:
{
union
{
PTRACE_TYPE_RET word;
gdb_byte byte[sizeof (PTRACE_TYPE_RET)];
} buffer;
ULONGEST rounded_offset;
LONGEST partial_len;
/* Round the start offset down to the next long word
boundary. */
rounded_offset = offset & -(ULONGEST) sizeof (PTRACE_TYPE_RET);
/* Since ptrace will transfer a single word starting at that
rounded_offset the partial_len needs to be adjusted down to
that (remember this function only does a single transfer).
Should the required length be even less, adjust it down
again. */
partial_len = (rounded_offset + sizeof (PTRACE_TYPE_RET)) - offset;
if (partial_len > len)
partial_len = len;
if (writebuf)
{
/* If OFFSET:PARTIAL_LEN is smaller than
ROUNDED_OFFSET:WORDSIZE then a read/modify write will
be needed. Read in the entire word. */
if (rounded_offset < offset
|| (offset + partial_len
< rounded_offset + sizeof (PTRACE_TYPE_RET)))
{
/* Need part of initial word -- fetch it. */
if (arch64)
buffer.word = rs6000_ptrace64 (PT_READ_I, pid,
rounded_offset, 0, NULL);
else
buffer.word = rs6000_ptrace32 (PT_READ_I, pid,
(int *) (uintptr_t)
rounded_offset,
0, NULL);
}
/* Copy data to be written over corresponding part of
buffer. */
memcpy (buffer.byte + (offset - rounded_offset),
writebuf, partial_len);
errno = 0;
if (arch64)
rs6000_ptrace64 (PT_WRITE_D, pid,
rounded_offset, buffer.word, NULL);
else
rs6000_ptrace32 (PT_WRITE_D, pid,
(int *) (uintptr_t) rounded_offset,
buffer.word, NULL);
if (errno)
return TARGET_XFER_EOF;
}
if (readbuf)
{
errno = 0;
if (arch64)
buffer.word = rs6000_ptrace64 (PT_READ_I, pid,
rounded_offset, 0, NULL);
else
buffer.word = rs6000_ptrace32 (PT_READ_I, pid,
(int *)(uintptr_t)rounded_offset,
0, NULL);
if (errno)
return TARGET_XFER_EOF;
/* Copy appropriate bytes out of the buffer. */
memcpy (readbuf, buffer.byte + (offset - rounded_offset),
partial_len);
}
*xfered_len = (ULONGEST) partial_len;
return TARGET_XFER_OK;
}
default:
return TARGET_XFER_E_IO;
}
}
static void
store_register (struct regcache *regcache, int regno)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
int addr[MAX_REGISTER_SIZE];
int nr, isfloat;
/* Fetch the register's value from the register cache. */
regcache_raw_collect (regcache, regno, addr);
/* -1 can be a successful return value, so infer errors from errno. */
errno = 0;
nr = regmap (gdbarch, regno, &isfloat);
/* Floating-point registers. */
if (isfloat)
rs6000_ptrace32 (PT_WRITE_FPR, PIDGET (inferior_ptid), addr, nr, 0);
/* Bogus register number. */
else if (nr < 0)
{
if (regno >= gdbarch_num_regs (gdbarch))
fprintf_unfiltered (gdb_stderr,
"gdb error: register no %d not implemented.\n",
regno);
}
/* Fixed-point registers. */
else
{
if (regno == gdbarch_sp_regnum (gdbarch))
/* Execute one dummy instruction (which is a breakpoint) in inferior
process to give kernel a chance to do internal housekeeping.
Otherwise the following ptrace(2) calls will mess up user stack
since kernel will get confused about the bottom of the stack
(%sp). */
exec_one_dummy_insn (regcache);
/* The PT_WRITE_GPR operation is rather odd. For 32-bit inferiors,
the register's value is passed by value, but for 64-bit inferiors,
the address of a buffer containing the value is passed. */
if (!ARCH64 ())
rs6000_ptrace32 (PT_WRITE_GPR, PIDGET (inferior_ptid), (int *)nr, *addr, 0);
else
{
/* PT_WRITE_GPR requires the buffer parameter to point to an 8-byte
area, even if the register is really only 32 bits. */
long long buf;
if (register_size (gdbarch, regno) == 8)
memcpy (&buf, addr, 8);
else
buf = *addr;
rs6000_ptrace64 (PT_WRITE_GPR, PIDGET (inferior_ptid), nr, 0, &buf);
}
}
if (errno)
{
perror ("ptrace write");
errno = 0;
}
}
int
child_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len,
int write, struct mem_attrib *attrib,
struct target_ops *target)
{
/* Round starting address down to 32-bit word boundary. */
int mask = sizeof (int) - 1;
CORE_ADDR addr = memaddr & ~(CORE_ADDR)mask;
/* Round ending address up to 32-bit word boundary. */
int count = ((memaddr + len - addr + mask) & ~(CORE_ADDR)mask)
/ sizeof (int);
/* Allocate word transfer buffer. */
/* FIXME (alloca): This code, cloned from infptrace.c, is unsafe
because it uses alloca to allocate a buffer of arbitrary size.
For very large xfers, this could crash GDB's stack. */
int *buf = (int *) alloca (count * sizeof (int));
int arch64 = ARCH64 ();
int i;
if (!write)
{
/* Retrieve memory a word at a time. */
for (i = 0; i < count; i++, addr += sizeof (int))
{
if (!read_word (addr, buf + i, arch64))
return 0;
QUIT;
}
/* Copy memory to supplied buffer. */
addr -= count * sizeof (int);
memcpy (myaddr, (char *)buf + (memaddr - addr), len);
}
else
{
/* Fetch leading memory needed for alignment. */
if (addr < memaddr)
if (!read_word (addr, buf, arch64))
return 0;
/* Fetch trailing memory needed for alignment. */
if (addr + count * sizeof (int) > memaddr + len)
if (!read_word (addr + (count - 1) * sizeof (int),
buf + count - 1, arch64))
return 0;
/* Copy supplied data into memory buffer. */
memcpy ((char *)buf + (memaddr - addr), myaddr, len);
/* Store memory one word at a time. */
for (i = 0, errno = 0; i < count; i++, addr += sizeof (int))
{
if (arch64)
rs6000_ptrace64 (PT_WRITE_D, PIDGET (inferior_ptid), addr, buf[i], NULL);
else
rs6000_ptrace32 (PT_WRITE_D, PIDGET (inferior_ptid), (int *)(long) addr,
buf[i], NULL);
if (errno)
return 0;
QUIT;
}
}
return len;
}
