void rt2x00_init_eeprom(struct _rt2x00_pci * rt2x00pci, struct _rt2x00_config * config) {
u32 reg = 0x00000000;
u16 eeprom = 0x0000;
u16 val_a = 0x0000;
u16 val_b = 0x0000;
/*
* 1 - Detect EEPROM width.
*/
rt2x00_register_read(rt2x00pci, CSR21, ®);
rt2x00pci->eeprom_width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? EEPROM_WIDTH_93c46 : EEPROM_WIDTH_93c66;
/*
* 2 - Identify rf chipset.
*/
eeprom = rt2x00_eeprom_read_word(rt2x00pci, EEPROM_ANTENNA);
set_chip(&rt2x00pci->chip, RT2560, rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE));
/*
* 3 - Identify default antenna configuration.
*/
val_a = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
val_b = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
config->antenna_flags |= val_a;
config->antenna_flags |= val_b << 8;
if((config->antenna_flags & ANTENNA_TX) == 0)
config->antenna_flags |= ANTENNA_TX_DIV;
if((config->antenna_flags & ANTENNA_RX) == 0)
config->antenna_flags |= ANTENNA_RX_DIV;
/*
* 4 - Identify default geography configuration.
*/
/*
eeprom = rt2x00_eeprom_read_word(rt2x00pci, EEPROM_GEOGRAPHY);
config->user.geography = rt2x00_get_field16(reg, EEPROM_GEOGRAPHY_GEO);
*/
/*
* 5 - Read BBP data from EEPROM and store in private structure.
*/
memset(&rt2x00pci->eeprom, 0x00, sizeof(rt2x00pci->eeprom));
for(eeprom = 0; eeprom < EEPROM_BBP_SIZE; eeprom++)
rt2x00pci->eeprom[eeprom] = rt2x00_eeprom_read_word(rt2x00pci, EEPROM_BBP_START + eeprom);
}
static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
{
unsigned int i;
u16 eeprom;
u8 reg_id;
u8 value;
for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
rt2400pci_bbp_read(rt2x00dev, 0, &value);
if ((value != 0xff) && (value != 0x00))
goto continue_csr_init;
NOTICE(rt2x00dev, "Waiting for BBP register.\n");
udelay(REGISTER_BUSY_DELAY);
}
ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
return -EACCES;
continue_csr_init:
rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
for (i = 0; i < EEPROM_BBP_SIZE; i++) {
rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
if (eeprom != 0xffff && eeprom != 0x0000) {
reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
reg_id, value);
rt2400pci_bbp_write(rt2x00dev, reg_id, value);
}
}
DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
return 0;
}
static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
{
unsigned int i;
u16 eeprom;
u8 reg_id;
u8 value;
if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
return -EACCES;
rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
for (i = 0; i < EEPROM_BBP_SIZE; i++) {
rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
if (eeprom != 0xffff && eeprom != 0x0000) {
reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
rt2400pci_bbp_write(rt2x00dev, reg_id, value);
}
}
return 0;
}
static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
{
u32 reg;
u16 value;
u16 eeprom;
/*
* Read EEPROM word for configuration.
*/
rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
/*
* Identify RF chipset.
*/
value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
rt2x00pci_register_read(rt2x00dev, CSR0, ®);
rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
!rt2x00_rf(&rt2x00dev->chip, RF2421)) {
ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
return -ENODEV;
}
/*
* Identify default antenna configuration.
*/
rt2x00dev->hw->conf.antenna_sel_tx =
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
rt2x00dev->hw->conf.antenna_sel_rx =
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
/*
* Store led mode, for correct led behaviour.
*/
rt2x00dev->led_mode =
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
/*
* Detect if this device has an hardware controlled radio.
*/
#ifdef CONFIG_RT2400PCI_RFKILL
if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
__set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
#endif /* CONFIG_RT2400PCI_RFKILL */
/*
* Check if the BBP tuning should be enabled.
*/
if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
__set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
return 0;
}
static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
{
u32 reg;
u16 value;
u16 eeprom;
rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
rt2x00pci_register_read(rt2x00dev, CSR0, ®);
rt2x00_set_chip(rt2x00dev, RT2460, value,
rt2x00_get_field32(reg, CSR0_REVISION));
if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
return -ENODEV;
}
rt2x00dev->default_ant.tx =
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
rt2x00dev->default_ant.rx =
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
#ifdef CONFIG_RT2X00_LIB_LEDS
value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
if (value == LED_MODE_TXRX_ACTIVITY ||
value == LED_MODE_DEFAULT ||
value == LED_MODE_ASUS)
rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
LED_TYPE_ACTIVITY);
#endif
if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
__set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
__set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
return 0;
}
static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
{
u32 reg;
u16 value;
u16 eeprom;
/*
* Read EEPROM word for configuration.
*/
rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
/*
* Identify RF chipset.
*/
value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
rt2x00pci_register_read(rt2x00dev, CSR0, ®);
rt2x00_set_chip(rt2x00dev, RT2460, value,
rt2x00_get_field32(reg, CSR0_REVISION));
if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
return -ENODEV;
}
/*
* Identify default antenna configuration.
*/
rt2x00dev->default_ant.tx =
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
rt2x00dev->default_ant.rx =
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
/*
* When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
* I am not 100% sure about this, but the legacy drivers do not
* indicate antenna swapping in software is required when
* diversity is enabled.
*/
if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
/*
* Store led mode, for correct led behaviour.
*/
#ifdef CONFIG_RT2X00_LIB_LEDS
value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
if (value == LED_MODE_TXRX_ACTIVITY ||
value == LED_MODE_DEFAULT ||
value == LED_MODE_ASUS)
rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
LED_TYPE_ACTIVITY);
#endif /* CONFIG_RT2X00_LIB_LEDS */
/*
* Detect if this device has an hardware controlled radio.
*/
if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
__set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
/*
* Check if the BBP tuning should be enabled.
*/
if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
__set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
return 0;
}
static int
rt2x00_init_bbp(struct _rt2x00_pci *rt2x00pci) {
u8 reg_id = 0x00;
u8 value = 0x00;
u8 counter = 0x00;
for(counter = 0x00; counter < REGISTER_BUSY_COUNT; counter++){
rt2x00_bbp_regread(rt2x00pci, 0x00, &value);
if((value != 0xff) && (value != 0x00))
goto continue_csr_init;
NOTICE("Waiting for BBP register.\n");
}
ERROR("hardware problem, BBP register access failed, aborting.\n");
return -EACCES;
continue_csr_init:
rt2x00_bbp_regwrite(rt2x00pci, 3, 0x02);
rt2x00_bbp_regwrite(rt2x00pci, 4, 0x19);
rt2x00_bbp_regwrite(rt2x00pci, 14, 0x1c);
rt2x00_bbp_regwrite(rt2x00pci, 15, 0x30);
rt2x00_bbp_regwrite(rt2x00pci, 16, 0xac);
rt2x00_bbp_regwrite(rt2x00pci, 17, 0x48);
rt2x00_bbp_regwrite(rt2x00pci, 18, 0x18);
rt2x00_bbp_regwrite(rt2x00pci, 19, 0xff);
rt2x00_bbp_regwrite(rt2x00pci, 20, 0x1e);
rt2x00_bbp_regwrite(rt2x00pci, 21, 0x08);
rt2x00_bbp_regwrite(rt2x00pci, 22, 0x08);
rt2x00_bbp_regwrite(rt2x00pci, 23, 0x08);
rt2x00_bbp_regwrite(rt2x00pci, 24, 0x70);
rt2x00_bbp_regwrite(rt2x00pci, 25, 0x40);
rt2x00_bbp_regwrite(rt2x00pci, 26, 0x08);
rt2x00_bbp_regwrite(rt2x00pci, 27, 0x23);
rt2x00_bbp_regwrite(rt2x00pci, 30, 0x10);
rt2x00_bbp_regwrite(rt2x00pci, 31, 0x2b);
rt2x00_bbp_regwrite(rt2x00pci, 32, 0xb9);
rt2x00_bbp_regwrite(rt2x00pci, 34, 0x12);
rt2x00_bbp_regwrite(rt2x00pci, 35, 0x50);
rt2x00_bbp_regwrite(rt2x00pci, 39, 0xc4);
rt2x00_bbp_regwrite(rt2x00pci, 40, 0x02);
rt2x00_bbp_regwrite(rt2x00pci, 41, 0x60);
rt2x00_bbp_regwrite(rt2x00pci, 53, 0x10);
rt2x00_bbp_regwrite(rt2x00pci, 54, 0x18);
rt2x00_bbp_regwrite(rt2x00pci, 56, 0x08);
rt2x00_bbp_regwrite(rt2x00pci, 57, 0x10);
rt2x00_bbp_regwrite(rt2x00pci, 58, 0x08);
rt2x00_bbp_regwrite(rt2x00pci, 61, 0x6d);
rt2x00_bbp_regwrite(rt2x00pci, 62, 0x10);
DEBUG("Start reading EEPROM contents...\n");
for(counter = 0; counter < EEPROM_BBP_SIZE; counter++){
if(rt2x00pci->eeprom[counter] != 0xffff && rt2x00pci->eeprom[counter] != 0x0000){
reg_id = rt2x00_get_field16(rt2x00pci->eeprom[counter], EEPROM_BBP_REG_ID);
value = rt2x00_get_field16(rt2x00pci->eeprom[counter], EEPROM_BBP_VALUE);
DEBUG("BBP reg_id: 0x%02x, value: 0x%02x.\n", reg_id, value);
rt2x00_bbp_regwrite(rt2x00pci, reg_id, value);
}
}
DEBUG("...End of EEPROM contents.\n");
return 0;
}
