/* i2c_transfer --
* Initiate multiple-messages transfer over specified I2C bus or
* put request into queue if bus or some other resource is busy. (This
* is non-blocking function).
*
* PARAMETERS:
* bus - I2C bus number
* nmsg - number of messages
* msg - pointer to messages array
* done - function which is called when transfer is finished
* done_arg_ptr - arbitrary argument pointer passed to done funciton
*
* RETURNS:
* RTEMS_SUCCESSFUL if transfer initiated successfully, or error
* code if something failed.
*/
rtems_status_code
i2c_transfer(i2c_bus_number bus, int nmsg, i2c_message *msg,
i2c_transfer_done done, void * done_arg_ptr)
{
i2c_qel qel;
rtems_interrupt_level level;
if (bus >= I2C_NUMBER_OF_BUSES)
{
return RTEMS_INVALID_NUMBER;
}
if (msg == NULL)
{
return RTEMS_INVALID_ADDRESS;
}
qel.bus = bus;
qel.msg = msg;
qel.nmsg = nmsg;
qel.done = done;
qel.done_arg_ptr = done_arg_ptr;
rtems_interrupt_disable(level);
if ((tqueue_head + 1) % tqueue_size == tqueue_tail)
{
rtems_interrupt_enable(level);
return RTEMS_TOO_MANY;
}
memcpy(tqueue + tqueue_head, &qel, sizeof(qel));
tqueue_head = (tqueue_head + 1) % tqueue_size;
rtems_interrupt_enable(level);
i2cdrv_unload();
return RTEMS_SUCCESSFUL;
}
/*
* Send characters to device-specific code
*/
void
rtems_termios_puts (
const void *_buf, int len, struct rtems_termios_tty *tty)
{
const unsigned char *buf = _buf;
unsigned int newHead;
rtems_interrupt_level level;
rtems_status_code sc;
if (tty->device.outputUsesInterrupts == TERMIOS_POLLED) {
(*tty->device.write)(tty->minor, (void *)buf, len);
return;
}
newHead = tty->rawOutBuf.Head;
while (len) {
/*
* Performance improvement could be made here.
* Copy multiple bytes to raw buffer:
* if (len > 1) && (space to buffer end, or tail > 1)
* ncopy = MIN (len, space to buffer end or tail)
* memcpy (raw buffer, buf, ncopy)
* buf += ncopy
* len -= ncopy
*
* To minimize latency, the memcpy should be done
* with interrupts enabled.
*/
newHead = (newHead + 1) % tty->rawOutBuf.Size;
rtems_interrupt_disable (level);
while (newHead == tty->rawOutBuf.Tail) {
tty->rawOutBufState = rob_wait;
rtems_interrupt_enable (level);
sc = rtems_semaphore_obtain (tty->rawOutBuf.Semaphore,
RTEMS_WAIT,
RTEMS_NO_TIMEOUT);
if (sc != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred (sc);
rtems_interrupt_disable (level);
}
tty->rawOutBuf.theBuf[tty->rawOutBuf.Head] = *buf++;
tty->rawOutBuf.Head = newHead;
if (tty->rawOutBufState == rob_idle) {
/* check, whether XOFF has been received */
if (!(tty->flow_ctrl & FL_ORCVXOF)) {
(*tty->device.write)(tty->minor,
(char *)&tty->rawOutBuf.theBuf[tty->rawOutBuf.Tail],1);
}
else {
/* remember that output has been stopped due to flow ctrl*/
tty->flow_ctrl |= FL_OSTOP;
}
tty->rawOutBufState = rob_busy;
}
rtems_interrupt_enable (level);
len--;
}
}
static rtems_task ppp_rxdaemon(rtems_task_argument arg)
{
rtems_event_set events;
rtems_interrupt_level level;
struct ppp_softc *sc = (struct ppp_softc *)arg;
struct mbuf *mp = (struct mbuf *)0;
struct mbuf *m;
/* enter processing loop */
while ( 1 ) {
/* wait for event */
rtems_event_receive(RX_PACKET|RX_MBUF|RX_EMPTY,RTEMS_WAIT|RTEMS_EVENT_ANY,RTEMS_NO_TIMEOUT,&events);
if ( events & RX_EMPTY ) {
printf("RX: QUEUE is EMPTY\n");
events &= ~RX_EMPTY;
}
if ( events ) {
/* get the network semaphore */
rtems_bsdnet_semaphore_obtain();
/* check to see if new packet was received */
if ( events & RX_PACKET ) {
/* get received packet mbuf chain */
rtems_interrupt_disable(level);
IF_DEQUEUE(&sc->sc_rawq, m);
rtems_interrupt_enable(level);
/* ensure packet was retrieved */
if ( m != (struct mbuf *)0 ) {
/* process the received packet */
mp = ppp_inproc(sc, m);
}
}
/* allocate a new mbuf to replace one */
if ( mp == NULL ) {
pppallocmbuf(sc, &mp);
}
/* place mbuf on freeq */
rtems_interrupt_disable(level);
IF_ENQUEUE(&sc->sc_freeq, mp);
rtems_interrupt_enable(level);
mp = (struct mbuf *)0;
/* release the network semaphore */
rtems_bsdnet_semaphore_release();
/* check to see if queue is empty */
if ( sc->sc_rawq.ifq_head ) {
/* queue is not empty - post another event */
rtems_event_send(sc->sc_rxtask, RX_PACKET);
}
}
}
}
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
printk(" BSP_install_rtems_irq_handler %d\n", irq->name );
if (!isValidInterrupt(irq->name)) {
printk("Invalid interrupt vector %d\n",irq->name);
return 0;
}
/*
* Check if default handler is actually connected. If not issue an error.
* You must first get the current handler via i386_get_current_idt_entry
* and then disconnect it using i386_delete_idt_entry.
* RATIONALE : to always have the same transition by forcing the user
* to get the previous handler before accepting to disconnect.
*/
rtems_interrupt_disable(level);
if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
rtems_interrupt_enable(level);
printk("IRQ vector %d already connected\n",irq->name);
return 0;
}
/*
* store the data provided by user
*/
rtems_hdl_tbl[irq->name] = *irq;
rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
/* XXX -FIX ME !! */
if (is_pci_irq(irq->name)) {
/*
* Enable interrupt
*/
printk("is_pci_irq = TRUE - FIX THIS!\n");
}
if (is_processor_irq(irq->name)) {
/*
* Enable exception at processor level
*/
printk("is_processor_irq = TRUE : Fix This\n");
}
/*
* Enable interrupt on device
*/
if (irq->on) {
printk("Call 0x%x\n", irq->on );
irq->on(irq);
}
rtems_interrupt_enable(level);
return 1;
}
/*
* ------------------------ RTEMS Shared Irq Handler Mngt Routines ----------------
*/
int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
rtems_irq_connect_data* vchain;
printk(" BSP_install_rtems_shared_irq_handler %d\n", irq->name );
if (!isValidInterrupt(irq->name)) {
printk("Invalid interrupt vector %d\n",irq->name);
return 0;
}
rtems_interrupt_disable(level);
if ( (int)rtems_hdl_tbl[irq->name].next_handler == -1 ) {
rtems_interrupt_enable(level);
printk("IRQ vector %d already connected to an unshared handler\n",irq->name);
return 0;
}
vchain = (rtems_irq_connect_data*)malloc(sizeof(rtems_irq_connect_data));
/* save off topmost handler */
vchain[0]= rtems_hdl_tbl[irq->name];
/*
* store the data provided by user
*/
rtems_hdl_tbl[irq->name] = *irq;
/* link chain to new topmost handler */
rtems_hdl_tbl[irq->name].next_handler = (void *)vchain;
/*
* XXX FIX ME
*/
if (is_pci_irq(irq->name)) {
}
if (is_processor_irq(irq->name)) {
/*
* Enable exception at processor level
*/
}
/*
* Enable interrupt on device
*/
if (irq->on)
irq->on(irq);
rtems_interrupt_enable(level);
return 1;
}
rtems_status_code mpc83xx_ipic_set_mask(
rtems_vector_number vector,
rtems_vector_number mask_vector,
bool mask
)
{
uint8_t pos = 0;
mpc83xx_ipic_mask_t *mask_entry;
uint32_t *mask_reg;
rtems_interrupt_level level;
/* Parameter check */
if (!MPC83XX_IPIC_IS_VALID_VECTOR( vector) ||
!MPC83XX_IPIC_IS_VALID_VECTOR( mask_vector)) {
return RTEMS_INVALID_NUMBER;
} else if (vector == mask_vector) {
return RTEMS_RESOURCE_IN_USE;
}
/* Position and mask entry */
pos = mpc83xx_ipic_mask_position_table [mask_vector];
mask_entry = &mpc83xx_ipic_prio2mask [vector];
/* Mask register and position */
if (pos < 32) {
mask_reg = &mask_entry->simsr_mask [0];
} else if (pos < 64) {
pos -= 32;
mask_reg = &mask_entry->simsr_mask [1];
} else if (pos < 96) {
pos -= 64;
mask_reg = &mask_entry->semsr_mask;
} else if (pos < 128) {
pos -= 96;
mask_reg = &mask_entry->sermr_mask;
} else {
return RTEMS_NOT_IMPLEMENTED;
}
/* Mask or unmask */
if (mask) {
rtems_interrupt_disable( level);
*mask_reg &= ~(1 << pos);
rtems_interrupt_enable( level);
} else {
rtems_interrupt_disable( level);
*mask_reg |= 1 << pos;
rtems_interrupt_enable( level);
}
return RTEMS_SUCCESSFUL;
}
/*
* ------------------------ RTEMS Shared Irq Handler Mngt Routines ----------------
*/
int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
rtems_irq_connect_data* vchain;
if (!isValidInterrupt(irq->name)) {
printk("Invalid interrupt vector %d\n",irq->name);
return 0;
}
/* pre-allocate memory outside of critical section */
vchain = (rtems_irq_connect_data*)malloc(sizeof(rtems_irq_connect_data));
rtems_interrupt_disable(level);
if ( (int)rtems_hdl_tbl[irq->name].next_handler == -1 ) {
rtems_interrupt_enable(level);
printk("IRQ vector %d already connected to an unshared handler\n",irq->name);
free(vchain);
return 0;
}
/* save off topmost handler */
vchain[0]= rtems_hdl_tbl[irq->name];
/*
* store the data provided by user
*/
rtems_hdl_tbl[irq->name] = *irq;
/* link chain to new topmost handler */
rtems_hdl_tbl[irq->name].next_handler = (void *)vchain;
/*
* enable_irq_at_pic is supposed to ignore
* requests to disable interrupts outside
* of the range handled by the PIC
*/
BSP_enable_irq_at_pic(irq->name);
/*
* Enable interrupt on device
*/
if (irq->on)
irq->on(irq);
rtems_interrupt_enable(level);
return 1;
}
static rtems_isr interruptHandler(rtems_vector_number vector) {
bfin_isr_t *isr = NULL;
uint32_t sourceMask0 = 0;
uint32_t sourceMask1 = 0;
rtems_interrupt_level isrLevel;
rtems_interrupt_disable(isrLevel);
vector -= CEC_INTERRUPT_BASE_VECTOR;
if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) {
isr = vectors[vector].head;
sourceMask0 = *(uint32_t volatile *) SIC_ISR &
*(uint32_t volatile *) SIC_IMASK;
sourceMask1 = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) &
*(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH);
while (isr) {
if ((sourceMask0 & isr->mask0) || (sourceMask1 & isr->mask1)) {
isr->isr(isr->_arg);
sourceMask0 = *(uint32_t volatile *) SIC_ISR &
*(uint32_t volatile *) SIC_IMASK;
sourceMask1 = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) &
*(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH);
}
isr = isr->next;
}
}
rtems_interrupt_enable(isrLevel);
}
static BSP_START_TEXT_SECTION __attribute__((flatten)) rtems_status_code
lpc24xx_pin_set_input(
#ifdef ARM_MULTILIB_ARCH_V4
volatile uint32_t *pinsel,
uint32_t pinsel_mask,
uint32_t pinsel_value,
#else
volatile uint32_t *iocon,
lpc24xx_pin_range pin_range,
#endif
volatile uint32_t *fio_dir,
uint32_t fio_bit
)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
*fio_dir &= ~fio_bit;
#ifdef ARM_MULTILIB_ARCH_V4
*pinsel &= ~pinsel_mask;
#else
*iocon = IOCON_MODE(2) | IOCON_ADMODE | IOCON_FILTER;
#endif
rtems_interrupt_enable(level);
return RTEMS_SUCCESSFUL;
}
/*-------------------------------------------------------------------------+
| Function: BSP_irq_disable_at_i8259s
| Description: Mask IRQ line in appropriate PIC chip.
| Global Variables: i8259s_cache
| Arguments: vector_offset - number of IRQ line to mask.
| Returns: Nothing.
+--------------------------------------------------------------------------*/
int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine)
{
unsigned short mask;
rtems_interrupt_level level;
if ( ((int)irqLine < BSP_LOWEST_OFFSET) ||
((int)irqLine > BSP_MAX_ON_i8259S )
)
return 1;
rtems_interrupt_disable(level);
mask = 1 << irqLine;
i8259s_cache |= mask;
i8259s_super_imr |= mask;
if (irqLine < 8)
{
outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
}
else
{
outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
}
rtems_interrupt_enable(level);
return 0;
}
/*-------------------------------------------------------------------------+
| Function: BSP_irq_disable_at_i8259s
| Description: Mask IRQ line in appropriate PIC chip.
| Global Variables: i8259s_cache
| Arguments: vector_offset - number of IRQ line to mask.
| Returns: original state or -1 on error.
+--------------------------------------------------------------------------*/
int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine)
{
unsigned short mask;
rtems_interrupt_level level;
int rval;
if ( ((int)irqLine < BSP_ISA_IRQ_LOWEST_OFFSET) ||
((int)irqLine > BSP_ISA_IRQ_MAX_OFFSET)
)
return -1;
rtems_interrupt_disable(level);
mask = 1 << irqLine;
rval = i8259s_cache & mask ? 0 : 1;
i8259s_cache |= mask;
if (irqLine < 8)
{
outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
}
else
{
outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
}
rtems_interrupt_enable(level);
return rval;
}
/*=========================================================================*\
| Function: |
\*-------------------------------------------------------------------------*/
void mcdma_glue_irq_disable
(
/*-------------------------------------------------------------------------*\
| Purpose: |
| disable interrupt for given task number |
+---------------------------------------------------------------------------+
| Input Parameters: |
\*-------------------------------------------------------------------------*/
int mcdma_channo /* task number to disable */
)
/*-------------------------------------------------------------------------*\
| Return Value: |
| none |
\*=========================================================================*/
{
rtems_interrupt_level level;
if (0 != ((1UL<<mcdma_channo) & MCDMA_INT_BIT_IMPL)) {
rtems_interrupt_disable(level);
/*
* valid task number
* disable interrupt in mcdma mask
*/
MCDMA_INT_DISABLE(MCF548X_DMA_DIMR,mcdma_channo);
rtems_interrupt_enable(level);
}
}
/**
* Configures a PIO or a group of PIO to generate an interrupt on status
* change. The provided interrupt handler will be called with the triggering
* pin as its parameter (enabling different pin instances to share the same
* handler).
* \param pPin Pointer to a Pin instance.
* \param handler Interrupt handler function pointer.
* \param arg Pointer to interrupt handler argument
*/
void PIO_ConfigureIt(const Pin *pPin, void (*handler)(const Pin *, void *arg),
void *arg)
{
InterruptSource *pSource;
rtems_interrupt_level level;
TRACE_DEBUG("PIO_ConfigureIt()\n\r");
rtems_interrupt_disable(level);
if (_dwNumSources == MAX_INTERRUPT_SOURCES) {
bsp_fatal(ATSAM_FATAL_PIO_CONFIGURE_IT);
}
pSource = &(_aIntSources[_dwNumSources]);
pSource->pPin = pPin;
pSource->handler = handler;
pSource->arg = arg;
_dwNumSources++;
rtems_interrupt_enable(level);
/* Define new source */
TRACE_DEBUG("PIO_ConfigureIt: Defining new source #%d.\n\r", _dwNumSources);
}
int mpc5xx_set_exception (const rtems_raw_except_connect_data* except)
{
rtems_interrupt_level level;
if (!mpc5xx_vector_is_valid(except->exceptIndex)) {
return 0;
}
/*
* Check if default handler is actually connected. If not issue an error.
* You must first get the current handler via mpc5xx_get_current_exception
* and then disconnect it using mpc5xx_delete_exception.
* RATIONALE : to always have the same transition by forcing the user
* to get the previous handler before accepting to disconnect.
*/
if (exception_handler_table[except->exceptIndex] !=
default_raw_except_entry.hdl.raw_hdl) {
return 0;
}
rtems_interrupt_disable(level);
raw_except_table[except->exceptIndex] = *except;
exception_handler_table[except->exceptIndex] = except->hdl.raw_hdl;
if (except->on)
except->on(except);
rtems_interrupt_enable(level);
return 1;
}
/*
* set management stuff
*/
int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
{
int i;
rtems_interrupt_level level;
rtems_interrupt_disable(level);
/*
* store given configuration
*/
BSP_rtems_irq_config = config;
BSP_rtems_irq_tbl = BSP_rtems_irq_config->irqHdlTbl;
/*
* store any irq-like processor exceptions
*/
for (i = BSP_PROCESSOR_IRQ_LOWEST_OFFSET;
i < BSP_PROCESSOR_IRQ_MAX_OFFSET;
i++) {
if (BSP_rtems_irq_tbl[i].hdl != config->defaultEntry.hdl) {
if (BSP_rtems_irq_tbl[i].on != NULL) {
BSP_rtems_irq_tbl[i].on
(&(BSP_rtems_irq_tbl[i]));
}
}
else {
if (BSP_rtems_irq_tbl[i].off != NULL) {
BSP_rtems_irq_tbl[i].off
(&(BSP_rtems_irq_tbl[i]));
}
}
}
rtems_interrupt_enable(level);
return 1;
}
/*
* support functions for PCMCIA IDE IF
*/
bool mpc5200_pcmciaide_probe(int minor)
{
bool ide_card_plugged = false; /* assume: we don't have a card plugged in */
struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[GPT2]);
#ifdef MPC5200_BOARD_DP2
/* Deactivate RESET signal */
rtems_interrupt_level level;
rtems_interrupt_disable(level);
mpc5200.gpiowe |= GPIO_W_PIN_PSC1_4;
mpc5200.gpiowod &= ~GPIO_W_PIN_PSC1_4;
mpc5200.gpiowdd |= GPIO_W_PIN_PSC1_4;
mpc5200.gpiowdo |= GPIO_W_PIN_PSC1_4;
rtems_interrupt_enable(level);
/* FIXME */
volatile int i = 0;
while (++i < 20000000);
#endif
/* enable card detection on GPT2 */
gpt->emsel = (GPT_EMSEL_GPIO_IN | GPT_EMSEL_TIMER_MS_GPIO);
#if defined (MPC5200_BOARD_BRS5L)
/* Check for card detection (-CD0) */
if((gpt->status) & GPT_STATUS_PIN)
ide_card_plugged = false;
else
#endif
ide_card_plugged = true;
return ide_card_plugged;
}
void Shm_Unlock(
Shm_Locked_queue_Control *lq_cb
)
{
(void) PSIM.Semaphore.unlock;
rtems_interrupt_enable( level );
}
/* test bodies */
void test_interrupt_inline(void)
{
rtems_interrupt_level level;
rtems_attribute level_attribute, level_attribute_macro;
bool in_isr;
puts( "interrupt is in progress (use body)" );
in_isr = rtems_interrupt_is_in_progress();
if ( in_isr ) {
puts( "interrupt reported to be is in progress (body)" );
rtems_test_exit( 0 );
}
puts( "interrupt disable (use inline)" );
rtems_interrupt_disable( level );
puts( "interrupt flash (use inline)" );
rtems_interrupt_flash( level );
puts( "interrupt enable (use inline)" );
rtems_interrupt_enable( level );
puts( "interrupt level attribute (use inline)" );
level_attribute = rtems_interrupt_level_attribute( level );
level_attribute_macro = RTEMS_INTERRUPT_LEVEL(level);
if ( level_attribute_macro == level_attribute ) {
puts( "test case working.." );
}
}
/*
* console_outbyte_interrupts
*
* This routine transmits a character out.
*
* Input parameters:
* port - port to transmit character to
* ch - character to be transmitted
*
* Output parameters: NONE
*
* Return values: NONE
*/
void console_outbyte_interrupts(
const Port_85C30_info *Port,
char ch
)
{
Console_Protocol *protocol;
uint32_t isrlevel;
protocol = Port->Protocol;
/*
* If this is the first character then we need to prime the pump
*/
if ( protocol->Is_TX_active == false ) {
rtems_interrupt_disable( isrlevel );
protocol->Is_TX_active = true;
outbyte_polled_85c30( Port->ctrl, ch );
rtems_interrupt_enable( isrlevel );
return;
}
while ( Ring_buffer_Is_full( &protocol->TX_Buffer ) );
Ring_buffer_Add_character( &protocol->TX_Buffer, ch );
}
MC68681_STATIC ssize_t mc68681_write_support_int(
int minor,
const char *buf,
size_t len
)
{
uint32_t Irql;
uint32_t pMC68681_port;
setRegister_f setReg;
pMC68681_port = Console_Port_Tbl[minor]->ulCtrlPort2;
setReg = Console_Port_Tbl[minor]->setRegister;
/*
* We are using interrupt driven output and termios only sends us
* one character at a time.
*/
if ( !len )
return 0;
/*
* Put the character out and enable interrupts if necessary.
*/
rtems_interrupt_disable(Irql);
if ( Console_Port_Data[minor].bActive == FALSE ) {
Console_Port_Data[minor].bActive = TRUE;
mc68681_enable_interrupts(minor, MC68681_IMR_ENABLE_ALL);
}
(*setReg)(pMC68681_port, MC68681_TX_BUFFER, *buf);
rtems_interrupt_enable(Irql);
return 0;
}
/**
* @brief Checks if the module has power.
*
* @param has_power Power.
* @param index Index to shift.
* @param turn_on Turn on/off the power.
* @param level Interrupts value.
*/
static rtems_status_code check_power(
const bool has_power,
const unsigned index,
const bool turn_on,
rtems_interrupt_level level
)
{
rtems_status_code status_code = RTEMS_INVALID_NUMBER;
if ( index <= LPC176X_MODULE_BITS_COUNT ) {
if ( has_power ) {
rtems_interrupt_disable( level );
if ( turn_on ) {
LPC176X_SCB.pconp |= 1u << index;
} else {
LPC176X_SCB.pconp &= ~( 1u << index );
}
rtems_interrupt_enable( level );
}
/* else implies that the module has not power. Also,
there is nothing to do. */
status_code = RTEMS_SUCCESSFUL;
}
/* else implies an invalid index number. Also, the function
does not return successful. */
return status_code;
}
rtems_status_code qoriq_pic_set_priority(
rtems_vector_number vector,
int new_priority,
int *old_priority
)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
uint32_t old_vpr = 0;
if (bsp_interrupt_is_valid_vector(vector)) {
int offs = vpr_and_dr_offsets [vector] << 2;
volatile uint32_t *vpr = (volatile uint32_t *) &qoriq.pic + offs;
if (QORIQ_PIC_PRIORITY_IS_VALID(new_priority)) {
rtems_interrupt_level level;
rtems_interrupt_disable(level);
old_vpr = *vpr;
*vpr = VPR_PRIORITY_SET(old_vpr, (uint32_t) new_priority);
rtems_interrupt_enable(level);
} else if (new_priority < 0) {
old_vpr = *vpr;
} else {
sc = RTEMS_INVALID_PRIORITY;
}
} else {
sc = RTEMS_INVALID_ID;
}
if (old_priority != NULL) {
*old_priority = (int) VPR_PRIORITY_GET(old_vpr);
}
return sc;
}
/*
* Exception global init.
*
* Install exception handler pointers from the raw exception table into the
* exception handler table.
*/
int mpc5xx_init_exceptions (rtems_raw_except_global_settings* config)
{
unsigned i;
rtems_interrupt_level level;
/*
* store various accelerators
*/
raw_except_table = config->rawExceptHdlTbl;
local_settings = config;
default_raw_except_entry = config->defaultRawEntry;
rtems_interrupt_disable(level);
for (i = 0; i < NUM_EXCEPTIONS; i++) {
exception_handler_table[i] = raw_except_table[i].hdl.raw_hdl;
if (raw_except_table[i].hdl.raw_hdl != default_raw_except_entry.hdl.raw_hdl) {
if (raw_except_table[i].on)
raw_except_table[i].on(&raw_except_table[i]);
}
else {
if (raw_except_table[i].off)
raw_except_table[i].off(&raw_except_table[i]);
}
}
rtems_interrupt_enable(level);
return 1;
}
void bfin_interrupt_enable_global(int source, bool enable) {
int vector;
rtems_interrupt_level isrLevel;
for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++)
if ( (vectors[vector].mask0 & (1 << source) ) || \
(vectors[vector].mask1 & (1 << (source - SIC_ISR0_MAX)) ))
break;
if (vector < CEC_INTERRUPT_COUNT) {
rtems_interrupt_disable(isrLevel);
if ( SIC_ISR0_MAX > source ) {
if (enable)
globalMask0 |= 1 << source;
else
globalMask0 &= ~(1 << source);
}else {
if (enable)
globalMask1 |= 1 << (source - SIC_ISR0_MAX);
else
globalMask1 &= ~(1 << (source - SIC_ISR0_MAX));
}
setMask(vector);
rtems_interrupt_enable(isrLevel);
}
}
static int
rtems_am29lv160_write_data_8 (volatile uint8_t* base,
uint32_t offset,
const uint8_t* data,
uint32_t size)
{
volatile uint8_t* seg = base + offset;
rtems_interrupt_level level;
/*
* Issue a reset.
*/
*base = 0xf0;
while (size)
{
rtems_interrupt_disable (level);
*(base + 0xaaa) = 0xaa;
*(base + 0x555) = 0x55;
*(base + 0xaaa) = 0xa0;
*seg = *data++;
rtems_interrupt_enable (level);
if (rtems_am29lv160_toggle_wait_8 (seg++) != 0)
return EIO;
size--;
}
/*
* Issue a reset.
*/
*base = 0xf0;
return 0;
}
void bfin_interrupt_enable_all(int source, bool enable) {
rtems_interrupt_level isrLevel;
int vector;
bfin_isr_t *walk;
for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++)
if ( (vectors[vector].mask0 & (1 << source) ) || \
(vectors[vector].mask1 & (1 << (source - SIC_ISR0_MAX)) ))
break;
if (vector < CEC_INTERRUPT_COUNT) {
rtems_interrupt_disable(isrLevel);
walk = vectors[vector].head;
while (walk) {
walk->mask0 = enable ? (1 << source) : 0;
walk = walk->next;
}
walk = vectors[vector].head;
while (walk) {
walk->mask1 = enable ? (1 << (source - SIC_ISR0_MAX)) : 0;
walk = walk->next;
}
setMask(vector);
rtems_interrupt_enable(isrLevel);
}
}
rtems_device_driver Clock_control(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp
)
{
uint32_t isrlevel;
rtems_libio_ioctl_args_t *args = pargp;
if (args == 0)
goto done;
/*
* This is hokey, but until we get a defined interface
* to do this, it will just be this simple...
*/
if (args->command == rtems_build_name('I', 'S', 'R', ' '))
{
Clock_isr(Clock_driver_vector);
}
else if (args->command == rtems_build_name('N', 'E', 'W', ' '))
{
rtems_interrupt_disable( isrlevel );
(void) set_vector( args->buffer, Clock_driver_vector, 1 );
rtems_interrupt_enable( isrlevel );
}
done:
return RTEMS_SUCCESSFUL;
}
/* add an ISR to the list for whichever vector it belongs to */
void bfin_interrupt_register(bfin_isr_t *isr) {
bfin_isr_t *walk;
rtems_interrupt_level isrLevel;
/* find the appropriate vector */
for (isr->vector = 0; isr->vector < CEC_INTERRUPT_COUNT; isr->vector++)
if (vectors[isr->vector].mask & (1 << isr->source))
break;
if (isr->vector < CEC_INTERRUPT_COUNT) {
isr->next = NULL;
isr->mask = 0;
rtems_interrupt_disable(isrLevel);
/* find the current end of the list */
walk = vectors[isr->vector].head;
while (walk && walk->next)
walk = walk->next;
/* append new isr to list */
if (walk)
walk->next = isr;
else
vectors[isr->vector].head = isr;
rtems_interrupt_enable(isrLevel);
} else
/* we failed, but make vector a legal value so other calls into
this module with this isr descriptor won't do anything bad */
isr->vector = 0;
}
static void compute_i8259_masks_from_prio (void)
{
rtems_interrupt_level level;
unsigned int i;
unsigned int j;
rtems_interrupt_disable(level);
/*
* Always mask at least current interrupt to prevent re-entrance
*/
for (i=0; i < BSP_IRQ_LINES_NUMBER; i++) {
* ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
for (j = 0; j < BSP_IRQ_LINES_NUMBER; j++) {
/*
* Mask interrupts at i8259 level that have a lower priority
*/
if (irqPrioTable [i] > irqPrioTable [j]) {
* ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j);
}
}
}
rtems_interrupt_enable(level);
}
rtems_task High_task(
rtems_task_argument argument
)
{
rtems_interrupt_level level;
benchmark_timer_initialize();
rtems_interrupt_disable( level );
isr_disable_time = benchmark_timer_read();
benchmark_timer_initialize();
rtems_interrupt_flash( level );
isr_flash_time = benchmark_timer_read();
benchmark_timer_initialize();
rtems_interrupt_enable( level );
isr_enable_time = benchmark_timer_read();
benchmark_timer_initialize();
_Thread_Disable_dispatch();
thread_disable_dispatch_time = benchmark_timer_read();
benchmark_timer_initialize();
_Thread_Enable_dispatch();
thread_enable_dispatch_time = benchmark_timer_read();
benchmark_timer_initialize();
_Thread_Set_state( _Thread_Executing, STATES_SUSPENDED );
thread_set_state_time = benchmark_timer_read();
_Context_Switch_necessary = true;
benchmark_timer_initialize();
_Thread_Dispatch(); /* dispatches Middle_task */
}
