void rtl8723ae_dm_bt_bback_off_level( struct ieee80211_hw *hw, u8 type )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv( hw );
if ( type == BT_BB_BACKOFF_OFF ) {
RT_TRACE( rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[BT]BBBackOffLevel Off!\n" );
rtl_write_dword( rtlpriv, 0xc04, 0x3a05611 );
} else if ( type == BT_BB_BACKOFF_ON ) {
RT_TRACE( rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[BT]BBBackOffLevel On!\n" );
rtl_write_dword( rtlpriv, 0xc04, 0x3a07611 );
rtlpcipriv->bt_coexist.sw_coexist_all_off = false;
}
}
bool rtl92cu_phy_bb_config(struct ieee80211_hw *hw)
{
bool rtstatus = true;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
u16 regval;
u32 regval32;
u8 b_reg_hwparafile = 1;
_rtl92c_phy_init_bb_rf_register_definition(hw);
regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval | BIT(13) |
BIT(0) | BIT(1));
rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
if (IS_HARDWARE_TYPE_8192CE(rtlhal)) {
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
} else if (IS_HARDWARE_TYPE_8192CU(rtlhal)) {
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD |
FEN_BB_GLB_RSTn | FEN_BBRSTB);
}
regval32 = rtl_read_dword(rtlpriv, 0x87c);
rtl_write_dword(rtlpriv, 0x87c, regval32 & (~BIT(31)));
if (IS_HARDWARE_TYPE_8192CU(rtlhal))
rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
if (b_reg_hwparafile == 1)
rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
return rtstatus;
}
static void _rtl92su_hw_configure(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
u8 reg_bw_opmode = 0;
u32 reg_rrsr = 0;
u8 regtmp = 0;
reg_bw_opmode = BW_OPMODE_20MHZ;
reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
regtmp = rtl_read_byte(rtlpriv, REG_INIRTSMCS_SEL);
reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
rtl_write_dword(rtlpriv, REG_INIRTSMCS_SEL, reg_rrsr);
rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
rtl_write_byte(rtlpriv, REG_MLT, 0x8f);
/* For Min Spacing configuration. */
switch (rtlphy->rf_type) {
case RF_1T2R:
case RF_1T1R:
rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
break;
case RF_2T2R:
case RF_2T2R_GREEN:
rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
break;
}
rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
}
bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
{
bool rtstatus = true;
struct rtl_priv *rtlpriv = rtl_priv(hw);
u16 regval;
u32 regvaldw;
u8 reg_hwparafile = 1;
_rtl92c_phy_init_bb_rf_register_definition(hw);
regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
regval | BIT(13) | BIT(0) | BIT(1));
rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
FEN_BB_GLB_RSTn | FEN_BBRSTB);
rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
if (reg_hwparafile == 1)
rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
return rtstatus;
}
void rtl92ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 ledcfg;
RT_TRACE(COMP_LED, DBG_LOUD,
("LedAddr:%X ledpin =%d\n", REG_LEDCFG2, pled->ledpin));
switch (pled->ledpin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
ledcfg = rtl_read_dword(rtlpriv , REG_GPIO_PIN_CTRL) | ~BIT(21);
ledcfg &= ~BIT(29);
rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, ledcfg);
break;
case LED_PIN_LED1:
break;
default:
RT_TRACE(COMP_ERR, DBG_LOUD,
("switch case not process\n"));
break;
}
pled->b_ledon = false;
}
bool rtl_btc_is_disable_edca_turbo(struct rtl_priv *rtlpriv)
{
bool bt_change_edca = false;
u32 cur_edca_val;
u32 edca_bt_hs_uplink = 0x5ea42b, edca_bt_hs_downlink = 0x5ea42b;
u32 edca_hs;
u32 edca_addr = 0x504;
cur_edca_val = rtl_read_dword(rtlpriv, edca_addr);
if (halbtc_is_wifi_uplink(rtlpriv)) {
if (cur_edca_val != edca_bt_hs_uplink) {
edca_hs = edca_bt_hs_uplink;
bt_change_edca = true;
}
} else {
if (cur_edca_val != edca_bt_hs_downlink) {
edca_hs = edca_bt_hs_downlink;
bt_change_edca = true;
}
}
if (bt_change_edca)
rtl_write_dword(rtlpriv, edca_addr, edca_hs);
return true;
}
void rtl92ee_sw_led_on( struct ieee80211_hw *hw, struct rtl_led *pled )
{
u32 ledcfg;
struct rtl_priv *rtlpriv = rtl_priv( hw );
RT_TRACE( rtlpriv, COMP_LED, DBG_LOUD,
"LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin );
switch ( pled->ledpin ) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
ledcfg = rtl_read_dword( rtlpriv , REG_GPIO_PIN_CTRL );
ledcfg &= ~BIT( 13 );
ledcfg |= BIT( 21 );
ledcfg &= ~BIT( 29 );
rtl_write_dword( rtlpriv, REG_GPIO_PIN_CTRL, ledcfg );
break;
case LED_PIN_LED1:
break;
default:
RT_TRACE( rtlpriv, COMP_ERR, DBG_LOUD,
"switch case %#x not processed\n", pled->ledpin );
break;
}
pled->ledon = true;
}
void rtl8723ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 type)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
if (type == BT_AGCTABLE_OFF) {
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[BT]AGCTable Off!\n");
rtl_write_dword(rtlpriv, 0xc78, 0x641c0001);
rtl_write_dword(rtlpriv, 0xc78, 0x631d0001);
rtl_write_dword(rtlpriv, 0xc78, 0x621e0001);
rtl_write_dword(rtlpriv, 0xc78, 0x611f0001);
rtl_write_dword(rtlpriv, 0xc78, 0x60200001);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x32000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x71000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0xb0000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0xfc000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_G1, 0xfffff, 0x30355);
} else if (type == BT_AGCTABLE_ON) {
RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
"[BT]AGCTable On!\n");
rtl_write_dword(rtlpriv, 0xc78, 0x4e1c0001);
rtl_write_dword(rtlpriv, 0xc78, 0x4d1d0001);
rtl_write_dword(rtlpriv, 0xc78, 0x4c1e0001);
rtl_write_dword(rtlpriv, 0xc78, 0x4b1f0001);
rtl_write_dword(rtlpriv, 0xc78, 0x4a200001);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0xdc000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x90000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x51000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x12000);
rtl8723ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_G1, 0xfffff, 0x00355);
rtlpcipriv->bt_coexist.sw_coexist_all_off = false;
}
}
void stg_rtl_cam_reset_all_entry(struct ieee80211_hw *hw)
{
u32 ul_command;
struct rtl_priv *rtlpriv = rtl_priv(hw);
ul_command = BIT(31) | BIT(30);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
}
void odm_edca_turbo_check_ce(void *dm_void)
{
struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
u64 cur_txok_cnt = 0;
u64 cur_rxok_cnt = 0;
u32 edca_be_ul = 0x5ea42b;
u32 edca_be_dl = 0x5ea42b;
u32 edca_be = 0x5ea42b;
bool is_cur_rdlstate;
bool edca_turbo_on = false;
if (dm->wifi_test)
return;
if (!dm->is_linked) {
rtlpriv->dm.is_any_nonbepkts = false;
return;
}
if (rtlpriv->dm.dbginfo.num_non_be_pkt > 0x100)
rtlpriv->dm.is_any_nonbepkts = true;
rtlpriv->dm.dbginfo.num_non_be_pkt = 0;
cur_txok_cnt = rtlpriv->stats.txbytesunicast_inperiod;
cur_rxok_cnt = rtlpriv->stats.rxbytesunicast_inperiod;
/*b_bias_on_rx = false;*/
edca_turbo_on = ((!rtlpriv->dm.is_any_nonbepkts) &&
(!rtlpriv->dm.disable_framebursting)) ?
true :
false;
if (rtlpriv->mac80211.mode == WIRELESS_MODE_B)
goto label_exit;
if (edca_turbo_on) {
is_cur_rdlstate =
(cur_rxok_cnt > cur_txok_cnt * 4) ? true : false;
edca_be = is_cur_rdlstate ? edca_be_dl : edca_be_ul;
rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM_8822B, edca_be);
rtlpriv->dm.is_cur_rdlstate = is_cur_rdlstate;
rtlpriv->dm.current_turbo_edca = true;
} else {
if (rtlpriv->dm.current_turbo_edca) {
u8 tmp = AC0_BE;
rtlpriv->cfg->ops->set_hw_reg(rtlpriv->hw,
HW_VAR_AC_PARAM,
(u8 *)(&tmp));
rtlpriv->dm.current_turbo_edca = false;
}
}
label_exit:
rtlpriv->dm.is_any_nonbepkts = false;
}
void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw)
{
u16 value16;
u32 value32;
struct rtl_priv *rtlpriv = rtl_priv(hw);
/* Response Rate Set */
value32 = rtl_read_dword(rtlpriv, REG_RRSR);
value32 &= ~RATE_BITMAP_ALL;
value32 |= RATE_RRSR_CCK_ONLY_1M;
rtl_write_dword(rtlpriv, REG_RRSR, value32);
/* SIFS (used in NAV) */
value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
rtl_write_word(rtlpriv, REG_SPEC_SIFS, value16);
/* Retry Limit */
value16 = _LRL(0x30) | _SRL(0x30);
rtl_write_dword(rtlpriv, REG_RL, value16);
}
void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x99997631);
rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
/* init AMPDU aggregation number, tuning for Tx's TP, */
rtl_write_word(rtlpriv, 0x4CA, 0x0708);
}
void rtl92c_enable_interrupt(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
if (IS_HARDWARE_TYPE_8192CE(rtlhal)) {
rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] &
0xFFFFFFFF);
rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] &
0xFFFFFFFF);
} else {
rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] &
0xFFFFFFFF);
rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] &
0xFFFFFFFF);
}
}
static void _r92su_set_fw_reg(struct rtl_priv *rtlpriv, u32 cmd,
u32 val, bool with_val)
{
_r92su_fw_reg_ready(rtlpriv);
if (with_val)
rtl_write_dword(rtlpriv, RF_BB_CMD_DATA, val);
FW_CMD_IO_SET(rtlpriv, cmd);
_r92su_fw_reg_ready(rtlpriv);
}
void rtl92s_fw_iocmd_data(struct ieee80211_hw *hw, u32* cmd, u8 flag)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
if (flag == 0) {
/* set */
rtl_write_dword(rtlpriv, REG_IOCMD_DATA, *cmd);
} else {
/* query */
*cmd = rtl_read_dword(rtlpriv, REG_IOCMD_DATA);
}
}
int stg_rtl_cam_delete_one_entry(struct ieee80211_hw *hw,
u8 *mac_addr, u32 ul_key_id)
{
u32 ul_command;
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(COMP_SEC, DBG_DMESG, ("key_idx:%d\n", ul_key_id));
ul_command = ul_key_id * CAM_CONTENT_COUNT;
ul_command = ul_command | BIT(31) | BIT(16);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], 0);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
RT_TRACE(COMP_SEC, DBG_DMESG,
("stg_rtl_cam_delete_one_entry(): WRITE A4: %x\n", 0));
RT_TRACE(COMP_SEC, DBG_DMESG,
("stg_rtl_cam_delete_one_entry(): WRITE A0: %x\n",
ul_command));
return 0;
}
void stg_rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 ul_command;
u32 ul_content;
u32 ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
switch (rtlpriv->sec.pairwise_enc_algorithm) {
case WEP40_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_WEP40];
break;
case WEP104_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_WEP104];
break;
case TKIP_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_TKIP];
break;
case AESCCMP_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
break;
default:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
}
ul_content = (uc_index & 3) | ((u16) (ul_enc_algo) << 2);
ul_content |= BIT(15);
ul_command = CAM_CONTENT_COUNT * uc_index;
ul_command = ul_command | BIT(31) | BIT(16);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
RT_TRACE(COMP_SEC, DBG_DMESG,
("stg_rtl_cam_mark_invalid(): WRITE A4: %x\n", ul_content));
RT_TRACE(COMP_SEC, DBG_DMESG,
("stg_rtl_cam_mark_invalid(): WRITE A0: %x\n", ul_command));
}
int rtl8723_fw_free_to_go(struct ieee80211_hw *hw, bool is_8723be,
int max_count)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
int err = -EIO;
u32 counter = 0;
u32 value32;
do {
value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
} while ((counter++ < max_count) &&
(!(value32 & FWDL_CHKSUM_RPT)));
if (counter >= max_count) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"chksum report fail ! REG_MCUFWDL:0x%08x .\n",
value32);
goto exit;
}
RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
"Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32);
value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL) | MCUFWDL_RDY;
value32 &= ~WINTINI_RDY;
rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
if (is_8723be)
rtl8723be_firmware_selfreset(hw);
counter = 0;
do {
value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
if (value32 & WINTINI_RDY) {
RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
"Polling FW ready success!! REG_MCUFWDL:0x%08x .\n",
value32);
err = 0;
goto exit;
}
mdelay(FW_8192C_POLLING_DELAY);
} while (counter++ < max_count);
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n",
value32);
exit:
return err;
}
u8 rtl92s_fw_iocmd(struct ieee80211_hw *hw, const u32 cmd)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
int pollcount = 50;
rtl_write_dword(rtlpriv, REG_IOCMD_CTRL, cmd);
msleep(100);
while (rtl_read_dword(rtlpriv, REG_IOCMD_CTRL) && pollcount > 0) {
pollcount--;
msleep(20);
}
return !!pollcount;
}
void rtl92s_dm_init( struct ieee80211_hw *hw )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
rtlpriv->dm.undec_sm_pwdb = -1;
_rtl92s_dm_init_dynamic_txpower( hw );
rtl92s_dm_init_edca_turbo( hw );
_rtl92s_dm_init_rate_adaptive_mask( hw );
_rtl92s_dm_init_txpowertracking_thermalmeter( hw );
_rtl92s_dm_init_dig( hw );
rtl_write_dword( rtlpriv, WFM5, FW_CCA_CHK_ENABLE );
}
void rtl92c_set_qos(struct ieee80211_hw *hw, int aci)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
u32 u4b_ac_param;
rtl92c_dm_init_edca_turbo(hw);
u4b_ac_param = (u32) mac->ac[aci].aifs;
u4b_ac_param |=
((u32) le16_to_cpu(mac->ac[aci].cw_min) & 0xF) <<
AC_PARAM_ECW_MIN_OFFSET;
u4b_ac_param |=
((u32) le16_to_cpu(mac->ac[aci].cw_max) & 0xF) <<
AC_PARAM_ECW_MAX_OFFSET;
u4b_ac_param |= (u32) le16_to_cpu(mac->ac[aci].tx_op) <<
AC_PARAM_TXOP_OFFSET;
RT_TRACE(rtlpriv, COMP_QOS, DBG_LOUD, "queue:%x, ac_param:%x\n",
aci, u4b_ac_param);
switch (aci) {
case AC1_BK:
rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, u4b_ac_param);
break;
case AC0_BE:
rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param);
break;
case AC2_VI:
rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, u4b_ac_param);
break;
case AC3_VO:
rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, u4b_ac_param);
break;
default:
RT_ASSERT(false, "invalid aci: %d !\n", aci);
break;
}
}
void rtl92c_init_edca_param(struct ieee80211_hw *hw,
u16 queue, u16 txop, u8 cw_min, u8 cw_max, u8 aifs)
{
/* sequence: VO, VI, BE, BK ==> the same as 92C hardware design.
* referenc : enum nl80211_txq_q or ieee80211_set_wmm_default function.
*/
u32 value;
struct rtl_priv *rtlpriv = rtl_priv(hw);
value = (u32)aifs;
value |= ((u32)cw_min & 0xF) << 8;
value |= ((u32)cw_max & 0xF) << 12;
value |= (u32)txop << 16;
/* 92C hardware register sequence is the same as queue number. */
rtl_write_dword(rtlpriv, (REG_EDCA_VO_PARAM + (queue * 4)), value);
}
/* Turn on AAP (RCR:bit 0) for promicuous mode. */
void rtl92su_allow_all_destaddr(struct ieee80211_hw *hw,
bool allow_all_da, bool write_into_reg)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 reg_rcr = rtl_read_dword(rtlpriv, RCR);
if (allow_all_da) /* Set BIT0 */
reg_rcr |= RCR_AAP;
else /* Clear BIT0 */
reg_rcr &= ~RCR_AAP;
if (write_into_reg)
rtl_write_dword(rtlpriv, RCR, reg_rcr);
RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
"receive_config=0x%08X, write_into_reg=%d\n",
reg_rcr, write_into_reg);
}
static int rtl_proc_get_cam_register_1(char *page, char **start,
off_t offset, int count, int *eof, void *data)
{
struct ieee80211_hw *hw = data;
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 target_cmd = 0;
u32 target_val=0;
u8 entry_i=0;
u32 ulstatus;
int len = 0;
int i = 100, j = 0;
/* This dump the current register page */
len += snprintf(page + len, count - len,
"\n#################### SECURITY CAM (0-10) ##################\n ");
for (j = 0; j < 11; j++) {
len += snprintf(page + len, count - len, "\nD: %2x > ", j);
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
/* polling bit, and No Write enable, and address */
target_cmd = entry_i + CAM_CONTENT_COUNT * j;
target_cmd = target_cmd | BIT(31);
/* Check polling bit is clear */
while ((i--) >= 0) {
ulstatus = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM]);
if (ulstatus & BIT(31)) {
continue;
} else {
break;
}
}
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], target_cmd);
target_val = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[RCAMO]);
len += snprintf(page + len, count - len, "%8.8x ", target_val);
}
}
len += snprintf(page + len, count - len,"\n");
*eof = 1;
return len;
}
static int rtl_proc_get_cam_register_1(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 target_cmd = 0;
u32 target_val=0;
u8 entry_i=0;
u32 ulstatus;
int i = 100, j = 0;
/* This dump the current register page */
seq_puts(m,
"\n#################### SECURITY CAM (0-10) ##################\n ");
for (j = 0; j < 11; j++) {
seq_printf(m, "\nD: %2x > ", j);
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
/* polling bit, and No Write enable, and address */
target_cmd = entry_i + CAM_CONTENT_COUNT * j;
target_cmd = target_cmd | BIT(31);
/* Check polling bit is clear */
while ((i--) >= 0) {
ulstatus = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RWCAM]);
if (ulstatus & BIT(31)) {
continue;
} else {
break;
}
}
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_cmd);
target_val = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RCAMO]);
seq_printf(m, "%8.8x ", target_val);
}
}
seq_puts(m, "\n");
return 0;
}
static int rtl_proc_get_cam_register_3(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 target_cmd = 0;
u32 target_val = 0;
u8 entry_i = 0;
u32 ulstatus;
int i = 100, j = 0;
/* This dump the current register page */
seq_puts(m,
"\n################### SECURITY CAM (22-31) ##################\n ");
for (j = 22; j < TOTAL_CAM_ENTRY; j++) {
seq_printf(m, "\nD: %2x > ", j);
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
target_cmd = entry_i+CAM_CONTENT_COUNT*j;
target_cmd = target_cmd | BIT(31);
while ((i--) >= 0) {
ulstatus = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RWCAM]);
if (ulstatus & BIT(31)) {
continue;
} else {
break;
}
}
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_cmd);
target_val = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RCAMO]);
seq_printf(m, "%8.8x ", target_val);
}
}
seq_puts(m, "\n");
return 0;
}
/**
* writeLLT - LLT table write access
* @io: io callback
* @address: LLT logical address.
* @data: LLT data content
*
* Realtek hardware access function.
*
*/
bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
bool status = true;
long count = 0;
u32 value = _LLT_INIT_ADDR(address) |
_LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
do {
value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
break;
if (count > POLLING_LLT_THRESHOLD) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"Failed to polling write LLT done at address %d! _LLT_OP_VALUE(%x)\n",
address, _LLT_OP_VALUE(value));
status = false;
break;
}
} while (++count);
return status;
}
static void _rtl92s_dm_txpowertracking_callback_thermalmeter(
struct ieee80211_hw *hw )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_efuse *rtlefuse = rtl_efuse( rtl_priv( hw ) );
u8 thermalvalue = 0;
u32 fw_cmd = 0;
rtlpriv->dm.txpower_trackinginit = true;
thermalvalue = ( u8 )rtl_get_rfreg( hw, RF90_PATH_A, RF_T_METER, 0x1f );
RT_TRACE( rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
"Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermal meter 0x%x\n",
thermalvalue,
rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter );
if ( thermalvalue ) {
rtlpriv->dm.thermalvalue = thermalvalue;
if ( hal_get_firmwareversion( rtlpriv ) >= 0x35 ) {
rtl92s_phy_set_fw_cmd( hw, FW_CMD_TXPWR_TRACK_THERMAL );
} else {
fw_cmd = ( FW_TXPWR_TRACK_THERMAL |
( rtlpriv->efuse.thermalmeter[0] << 8 ) |
( thermalvalue << 16 ) );
RT_TRACE( rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
"Write to FW Thermal Val = 0x%x\n", fw_cmd );
rtl_write_dword( rtlpriv, WFM5, fw_cmd );
rtl92s_phy_chk_fwcmd_iodone( hw );
}
}
rtlpriv->dm.txpowercount = 0;
}
static void _rtl92s_dm_check_edca_turbo( struct ieee80211_hw *hw )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_mac *mac = rtl_mac( rtl_priv( hw ) );
static u64 last_txok_cnt;
static u64 last_rxok_cnt;
u64 cur_txok_cnt = 0;
u64 cur_rxok_cnt = 0;
u32 edca_be_ul = edca_setting_ul[mac->vendor];
u32 edca_be_dl = edca_setting_dl[mac->vendor];
u32 edca_gmode = edca_setting_dl_gmode[mac->vendor];
if ( mac->link_state != MAC80211_LINKED ) {
rtlpriv->dm.current_turbo_edca = false;
goto dm_checkedcaturbo_exit;
}
if ( ( !rtlpriv->dm.is_any_nonbepkts ) &&
( !rtlpriv->dm.disable_framebursting ) ) {
cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
if ( rtlpriv->phy.rf_type == RF_1T2R ) {
if ( cur_txok_cnt > 4 * cur_rxok_cnt ) {
/* Uplink TP is present. */
if ( rtlpriv->dm.is_cur_rdlstate ||
!rtlpriv->dm.current_turbo_edca ) {
rtl_write_dword( rtlpriv, EDCAPARA_BE,
edca_be_ul );
rtlpriv->dm.is_cur_rdlstate = false;
}
} else {/* Balance TP is present. */
if ( !rtlpriv->dm.is_cur_rdlstate ||
!rtlpriv->dm.current_turbo_edca ) {
if ( mac->mode == WIRELESS_MODE_G ||
mac->mode == WIRELESS_MODE_B )
rtl_write_dword( rtlpriv,
EDCAPARA_BE,
edca_gmode );
else
rtl_write_dword( rtlpriv,
EDCAPARA_BE,
edca_be_dl );
rtlpriv->dm.is_cur_rdlstate = true;
}
}
rtlpriv->dm.current_turbo_edca = true;
} else {
if ( cur_rxok_cnt > 4 * cur_txok_cnt ) {
if ( !rtlpriv->dm.is_cur_rdlstate ||
!rtlpriv->dm.current_turbo_edca ) {
if ( mac->mode == WIRELESS_MODE_G ||
mac->mode == WIRELESS_MODE_B )
rtl_write_dword( rtlpriv,
EDCAPARA_BE,
edca_gmode );
else
rtl_write_dword( rtlpriv,
EDCAPARA_BE,
edca_be_dl );
rtlpriv->dm.is_cur_rdlstate = true;
}
} else {
if ( rtlpriv->dm.is_cur_rdlstate ||
!rtlpriv->dm.current_turbo_edca ) {
rtl_write_dword( rtlpriv, EDCAPARA_BE,
edca_be_ul );
rtlpriv->dm.is_cur_rdlstate = false;
}
}
rtlpriv->dm.current_turbo_edca = true;
}
} else {
if ( rtlpriv->dm.current_turbo_edca ) {
u8 tmp = AC0_BE;
rtlpriv->cfg->ops->set_hw_reg( hw, HW_VAR_AC_PARAM,
&tmp );
rtlpriv->dm.current_turbo_edca = false;
}
}
dm_checkedcaturbo_exit:
rtlpriv->dm.is_any_nonbepkts = false;
last_txok_cnt = rtlpriv->stats.txbytesunicast;
last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
}
static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no,
u8 *mac_addr, u8 *key_cont_128, u16 us_config)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 target_command;
u32 target_content = 0;
u8 entry_i;
RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_DMESG, "Key content:",
key_cont_128, 16);
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
target_command = entry_i + CAM_CONTENT_COUNT * entry_no;
target_command = target_command | BIT(31) | BIT(16);
if (entry_i == 0) {
target_content = (u32) (*(mac_addr + 0)) << 16 |
(u32) (*(mac_addr + 1)) << 24 | (u32) us_config;
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
target_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_command);
RT_TRACE(COMP_SEC, DBG_LOUD,
("WRITE %x: %x\n",
rtlpriv->cfg->maps[WCAMI], target_content));
RT_TRACE(COMP_SEC, DBG_LOUD,
("The Key ID is %d\n", entry_no));
RT_TRACE(COMP_SEC, DBG_LOUD,
("WRITE %x: %x\n",
rtlpriv->cfg->maps[RWCAM], target_command));
} else if (entry_i == 1) {
target_content = (u32) (*(mac_addr + 5)) << 24 |
(u32) (*(mac_addr + 4)) << 16 |
(u32) (*(mac_addr + 3)) << 8 |
(u32) (*(mac_addr + 2));
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
target_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_command);
RT_TRACE(COMP_SEC, DBG_LOUD,
("WRITE A4: %x\n", target_content));
RT_TRACE(COMP_SEC, DBG_LOUD,
("WRITE A0: %x\n", target_command));
} else {
target_content =
(u32) (*(key_cont_128 + (entry_i * 4 - 8) + 3)) <<
24 | (u32) (*(key_cont_128 + (entry_i * 4 - 8) + 2))
<< 16 |
(u32) (*(key_cont_128 + (entry_i * 4 - 8) + 1)) << 8
| (u32) (*(key_cont_128 + (entry_i * 4 - 8) + 0));
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
target_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_command);
udelay(100);
RT_TRACE(COMP_SEC, DBG_LOUD,
("WRITE A4: %x\n", target_content));
RT_TRACE(COMP_SEC, DBG_LOUD,
("WRITE A0: %x\n", target_command));
}
}
RT_TRACE(COMP_SEC, DBG_LOUD,
("after set key, usconfig:%x\n", us_config));
}
