void
r88e_fw_reset(struct rtwn_softc *sc, int reason)
{
uint16_t reg;
reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN);
rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN);
}
void
r92cu_init_bb(struct rtwn_softc *sc)
{
/* Enable BB and RF. */
rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
R92C_SYS_FUNC_EN_DIO_RF);
rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
rtwn_write_1(sc, R92C_RF_CTRL,
R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
rtwn_write_1(sc, R92C_SYS_FUNC_EN,
R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
rtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f);
rtwn_write_1(sc, 0x15, 0xe9);
rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
r92c_init_bb_common(sc);
if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
R92C_HSSI_PARAM2_CCK_HIPWR)
sc->sc_flags |= RTWN_FLAG_CCK_HIPWR;
}
static int
r92c_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len)
{
struct r92c_fw_cmd cmd;
int ntries, error;
KASSERT(len <= sizeof(cmd.msg),
("%s: firmware command too long (%d > %zu)\n",
__func__, len, sizeof(cmd.msg)));
if (!(sc->sc_flags & RTWN_FW_LOADED)) {
RTWN_DPRINTF(sc, RTWN_DEBUG_FIRMWARE, "%s: firmware "
"was not loaded; command (id %u) will be discarded\n",
__func__, id);
return (0);
}
/* Wait for current FW box to be empty. */
for (ntries = 0; ntries < 50; ntries++) {
if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))
break;
rtwn_delay(sc, 2000);
}
if (ntries == 100) {
device_printf(sc->sc_dev,
"could not send firmware command\n");
return (ETIMEDOUT);
}
memset(&cmd, 0, sizeof(cmd));
cmd.id = id;
if (len > 3) {
/* Ext command: [id : byte2 : byte3 : byte4 : byte0 : byte1] */
cmd.id |= R92C_CMD_FLAG_EXT;
memcpy(cmd.msg, (const uint8_t *)buf + 2, len - 2);
memcpy(cmd.msg + 3, buf, 2);
} else
memcpy(cmd.msg, buf, len);
/* Write the first word last since that will trigger the FW. */
if (len > 3) {
error = rtwn_write_2(sc, R92C_HMEBOX_EXT(sc->fwcur),
*(uint16_t *)((uint8_t *)&cmd + 4));
if (error != 0)
return (error);
}
error = rtwn_write_4(sc, R92C_HMEBOX(sc->fwcur),
*(uint32_t *)&cmd);
if (error != 0)
return (error);
sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX;
return (0);
}
void
r12au_init_rx_agg(struct rtwn_softc *sc)
{
struct r12a_softc *rs = sc->sc_priv;
/* Rx aggregation (USB). */
rtwn_write_2(sc, R92C_RXDMA_AGG_PG_TH,
rs->ac_usb_dma_size | (rs->ac_usb_dma_time << 8));
rtwn_setbits_1(sc, R92C_TRXDMA_CTRL, 0,
R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
}
void
r12au_init_ampdu(struct rtwn_softc *sc)
{
struct r12a_softc *rs = sc->sc_priv;
/* Rx interval (USB3). */
rtwn_write_1(sc, 0xf050, 0x01);
/* burst length = 4 */
rtwn_write_2(sc, R92C_RXDMA_STATUS, 0x7400);
rtwn_write_1(sc, R92C_RXDMA_STATUS + 1, 0xf5);
/* Setup AMPDU aggregation. */
rtwn_write_1(sc, R12A_AMPDU_MAX_TIME, rs->ampdu_max_time);
rtwn_write_4(sc, R12A_AMPDU_MAX_LENGTH, 0xffffffff);
/* 80 MHz clock (again?) */
rtwn_write_1(sc, R92C_USTIME_TSF, 0x50);
rtwn_write_1(sc, R92C_USTIME_EDCA, 0x50);
rtwn_r12a_init_burstlen(sc);
/* Enable single packet AMPDU. */
rtwn_setbits_1(sc, R12A_HT_SINGLE_AMPDU, 0,
R12A_HT_SINGLE_AMPDU_PKT_ENA);
/* 11K packet length for VHT. */
rtwn_write_1(sc, R92C_RX_PKT_LIMIT, 0x18);
rtwn_write_1(sc, R92C_PIFS, 0);
rtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x1f1f);
rtwn_r12a_init_ampdu_fwhw(sc);
/* Do not reset MAC. */
rtwn_setbits_1(sc, R92C_RSV_CTRL, 0, 0x60);
r12au_arfb_init(sc);
}
int
r92cu_power_on(struct rtwn_softc *sc)
{
#define RTWN_CHK(res) do { \
if (res != 0) \
return (EIO); \
} while(0)
uint32_t reg;
int ntries;
/* Wait for autoload done bit. */
for (ntries = 0; ntries < 5000; ntries++) {
if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
break;
rtwn_delay(sc, 10);
}
if (ntries == 5000) {
device_printf(sc->sc_dev,
"timeout waiting for chip autoload\n");
return (ETIMEDOUT);
}
/* Unlock ISO/CLK/Power control register. */
RTWN_CHK(rtwn_write_1(sc, R92C_RSV_CTRL, 0));
/* Move SPS into PWM mode. */
RTWN_CHK(rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b));
/* just in case if power_off() was not properly executed. */
rtwn_delay(sc, 100);
reg = rtwn_read_1(sc, R92C_LDOV12D_CTRL);
if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {
RTWN_CHK(rtwn_write_1(sc, R92C_LDOV12D_CTRL,
reg | R92C_LDOV12D_CTRL_LDV12_EN));
rtwn_delay(sc, 100);
RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_ISO_CTRL,
R92C_SYS_ISO_CTRL_MD2PP, 0));
}
/* Auto enable WLAN. */
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
R92C_APS_FSMCO_APFM_ONMAC, 1));
for (ntries = 0; ntries < 5000; ntries++) {
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
R92C_APS_FSMCO_APFM_ONMAC))
break;
rtwn_delay(sc, 10);
}
if (ntries == 5000) {
device_printf(sc->sc_dev,
"timeout waiting for MAC auto ON\n");
return (ETIMEDOUT);
}
/* Enable radio, GPIO and LED functions. */
RTWN_CHK(rtwn_write_2(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_AFSM_HSUS |
R92C_APS_FSMCO_PDN_EN |
R92C_APS_FSMCO_PFM_ALDN));
/* Release RF digital isolation. */
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_SYS_ISO_CTRL,
R92C_SYS_ISO_CTRL_DIOR, 0, 1));
/* Initialize MAC. */
RTWN_CHK(rtwn_setbits_1(sc, R92C_APSD_CTRL,
R92C_APSD_CTRL_OFF, 0));
for (ntries = 0; ntries < 1000; ntries++) {
if (!(rtwn_read_1(sc, R92C_APSD_CTRL) &
R92C_APSD_CTRL_OFF_STATUS))
break;
rtwn_delay(sc, 50);
}
if (ntries == 1000) {
device_printf(sc->sc_dev,
"timeout waiting for MAC initialization\n");
return (ETIMEDOUT);
}
/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
R92C_CR_CALTMR_EN));
RTWN_CHK(rtwn_write_1(sc, 0xfe10, 0x19));
return (0);
#undef RTWN_CHK
}
void
r92cu_power_off(struct rtwn_softc *sc)
{
#ifndef RTWN_WITHOUT_UCODE
struct r92c_softc *rs = sc->sc_priv;
#endif
uint32_t reg;
int error;
/* Deinit C2H event handler. */
#ifndef RTWN_WITHOUT_UCODE
callout_stop(&rs->rs_c2h_report);
rs->rs_c2h_paused = 0;
rs->rs_c2h_pending = 0;
rs->rs_c2h_timeout = hz;
#endif
/* Block all Tx queues. */
error = rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
if (error == ENXIO) /* hardware gone */
return;
/* Disable RF */
rtwn_rf_write(sc, 0, 0, 0);
rtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF);
/* Reset BB state machine */
rtwn_write_1(sc, R92C_SYS_FUNC_EN,
R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA |
R92C_SYS_FUNC_EN_BB_GLB_RST);
rtwn_write_1(sc, R92C_SYS_FUNC_EN,
R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA);
/*
* Reset digital sequence
*/
#ifndef RTWN_WITHOUT_UCODE
if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) {
/* Reset MCU ready status */
rtwn_write_1(sc, R92C_MCUFWDL, 0);
/* If firmware in ram code, do reset */
r92c_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
}
#endif
/* Reset MAC and Enable 8051 */
rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1,
(R92C_SYS_FUNC_EN_CPUEN |
R92C_SYS_FUNC_EN_ELDR |
R92C_SYS_FUNC_EN_HWPDN) >> 8);
/* Reset MCU ready status */
rtwn_write_1(sc, R92C_MCUFWDL, 0);
/* Disable MAC clock */
rtwn_write_2(sc, R92C_SYS_CLKR,
R92C_SYS_CLKR_ANAD16V_EN |
R92C_SYS_CLKR_ANA8M |
R92C_SYS_CLKR_LOADER_EN |
R92C_SYS_CLKR_80M_SSC_DIS |
R92C_SYS_CLKR_SYS_EN |
R92C_SYS_CLKR_RING_EN |
0x4000);
/* Disable AFE PLL */
rtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80);
/* Gated AFE DIG_CLOCK */
rtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F);
/* Isolated digital to PON */
rtwn_write_1(sc, R92C_SYS_ISO_CTRL,
R92C_SYS_ISO_CTRL_MD2PP |
R92C_SYS_ISO_CTRL_PA2PCIE |
R92C_SYS_ISO_CTRL_PD2CORE |
R92C_SYS_ISO_CTRL_IP2MAC |
R92C_SYS_ISO_CTRL_DIOP |
R92C_SYS_ISO_CTRL_DIOE);
/*
* Pull GPIO PIN to balance level and LED control
*/
/* 1. Disable GPIO[7:0] */
rtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000);
reg = rtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00;
reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000;
rtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg);
/* Disable GPIO[10:8] */
rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x00);
reg = rtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0;
reg |= (((reg & 0x000f) << 4) | 0x0780);
rtwn_write_2(sc, R92C_GPIO_IO_SEL, reg);
/* Disable LED0 & 1 */
rtwn_write_2(sc, R92C_LEDCFG0, 0x8080);
/*
* Reset digital sequence
*/
/* Disable ELDR clock */
rtwn_write_2(sc, R92C_SYS_CLKR,
R92C_SYS_CLKR_ANAD16V_EN |
R92C_SYS_CLKR_ANA8M |
R92C_SYS_CLKR_LOADER_EN |
R92C_SYS_CLKR_80M_SSC_DIS |
R92C_SYS_CLKR_SYS_EN |
R92C_SYS_CLKR_RING_EN |
0x4000);
/* Isolated ELDR to PON */
rtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1,
(R92C_SYS_ISO_CTRL_DIOR |
R92C_SYS_ISO_CTRL_PWC_EV12V) >> 8);
/*
* Disable analog sequence
*/
/* Disable A15 power */
rtwn_write_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_OBUF);
/* Disable digital core power */
rtwn_setbits_1(sc, R92C_LDOV12D_CTRL,
R92C_LDOV12D_CTRL_LDV12_EN, 0);
/* Enter PFM mode */
rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23);
/* Set USB suspend */
rtwn_write_2(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_APDM_HOST |
R92C_APS_FSMCO_AFSM_HSUS |
R92C_APS_FSMCO_PFM_ALDN);
/* Lock ISO/CLK/Power control register. */
rtwn_write_1(sc, R92C_RSV_CTRL, 0x0E);
}
int
r12a_power_on(struct rtwn_softc *sc)
{
#define RTWN_CHK(res) do { \
if (res != 0) \
return (EIO); \
} while(0)
int ntries;
r12a_rf_init_workaround(sc);
/* Force PWM mode. */
RTWN_CHK(rtwn_setbits_1(sc, R92C_SPS0_CTRL + 1, 0, 0x01));
/* Turn off ZCD. */
RTWN_CHK(rtwn_setbits_2(sc, 0x014, 0x0180, 0));
/* Enable LDO normal mode. */
RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP,
0));
/* GPIO 0...7 input mode. */
RTWN_CHK(rtwn_write_1(sc, R92C_GPIO_IOSEL, 0));
/* GPIO 11...8 input mode. */
RTWN_CHK(rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0));
/* Enable WL suspend. */
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_AFSM_HSUS, 0, 1));
/* Enable 8051. */
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
0, R92C_SYS_FUNC_EN_CPUEN, 1));
/* Disable SW LPS. */
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_APFM_RSM, 0, 1));
/* Wait for power ready bit. */
for (ntries = 0; ntries < 5000; ntries++) {
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
break;
rtwn_delay(sc, 10);
}
if (ntries == 5000) {
device_printf(sc->sc_dev,
"timeout waiting for chip power up\n");
return (ETIMEDOUT);
}
/* Disable WL suspend. */
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_AFSM_HSUS, 0, 1));
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
R92C_APS_FSMCO_APFM_ONMAC, 1));
for (ntries = 0; ntries < 5000; ntries++) {
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
R92C_APS_FSMCO_APFM_ONMAC))
break;
rtwn_delay(sc, 10);
}
if (ntries == 5000)
return (ETIMEDOUT);
/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000));
RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
R92C_CR_CALTMR_EN));
return (0);
}
int
r88ee_power_on(struct rtwn_softc *sc)
{
int ntries;
/* Disable XTAL output for power saving. */
rtwn_setbits_1(sc, R88E_XCK_OUT_CTRL, R88E_XCK_OUT_CTRL_EN, 0);
/* Unlock ISO/CLK/Power control register. */
rtwn_setbits_2(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_APDM_HPDN, 0);
rtwn_write_1(sc, R92C_RSV_CTRL, 0);
/* Wait for power ready bit */
for(ntries = 0; ntries < 5000; ntries++) {
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
break;
rtwn_delay(sc, 10);
}
if (ntries == 5000) {
device_printf(sc->sc_dev,
"timeout waiting for chip power up\n");
return (ETIMEDOUT);
}
/* Reset BB. */
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
/* schmit trigger */
rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
/* Disable HWPDN. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_APDM_HPDN, 0, 1);
/* Disable WL suspend. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1);
/* Auto-enable WLAN */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
0, R92C_APS_FSMCO_APFM_ONMAC, 1);
for (ntries = 0; ntries < 5000; ntries++) {
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
R92C_APS_FSMCO_APFM_ONMAC))
break;
rtwn_delay(sc, 10);
}
if (ntries == 5000)
return (ETIMEDOUT);
rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
/* Enable LDO normal mode. */
rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP, 0);
rtwn_setbits_1(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_PDN_EN);
rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL_EXT + 1, 0, 0x02);
rtwn_setbits_1(sc, R92C_SYS_CLKR, 0, 0x08);
rtwn_setbits_2(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_ENSIC, 0);
/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
rtwn_write_2(sc, R92C_CR, 0);
rtwn_setbits_2(sc, R92C_CR, 0,
R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
R92C_CR_CALTMR_EN);
rtwn_write_4(sc, R92C_INT_MIG, 0);
rtwn_write_4(sc, R92C_MCUTST_1, 0);
return (0);
}