rtx
gen_rtx_fmt_iuuBieiee (RTX_CODE code, enum machine_mode mode,
int arg0,
rtx arg1,
rtx arg2,
struct basic_block_def *arg3,
int arg4,
rtx arg5,
int arg6,
rtx arg7,
rtx arg8)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XINT (rt, 0) = arg0;
XEXP (rt, 1) = arg1;
XEXP (rt, 2) = arg2;
XBBDEF (rt, 3) = arg3;
XINT (rt, 4) = arg4;
XEXP (rt, 5) = arg5;
XINT (rt, 6) = arg6;
XEXP (rt, 7) = arg7;
XEXP (rt, 8) = arg8;
return rt;
}
rtx
gen_rtx_CONST_INT (enum machine_mode mode ATTRIBUTE_UNUSED,
HOST_WIDE_INT arg)
{
rtx rt = rtx_alloc (CONST_INT);
XWINT (rt, 0) = arg;
return rt;
}
rtx
gen_rtx_CONST_INT (enum machine_mode ARG_UNUSED (mode),
HOST_WIDE_INT arg)
{
rtx rt = rtx_alloc (CONST_INT);
XWINT (rt, 0) = arg;
return rt;
}
static void
test_dumping_rtx_reuse ()
{
rtx_reuse_manager r;
rtx x = rtx_alloc (SCRATCH);
rtx y = rtx_alloc (SCRATCH);
rtx z = rtx_alloc (SCRATCH);
/* x and y will be seen more than once. */
r.preprocess (x);
r.preprocess (x);
r.preprocess (y);
r.preprocess (y);
/* z will be only seen once. */
r.preprocess (z);
/* Verify that x and y have been assigned reuse IDs. */
int reuse_id_for_x;
ASSERT_TRUE (r.has_reuse_id (x, &reuse_id_for_x));
ASSERT_EQ (0, reuse_id_for_x);
int reuse_id_for_y;
ASSERT_TRUE (r.has_reuse_id (y, &reuse_id_for_y));
ASSERT_EQ (1, reuse_id_for_y);
/* z is only seen once and thus shouldn't get a reuse ID. */
ASSERT_FALSE (r.has_reuse_id (z, NULL));
/* The first dumps of x and y should be prefixed by reuse ID;
all subsequent dumps of them should show up as "reuse_rtx". */
ASSERT_RTL_DUMP_EQ_WITH_REUSE ("(0|scratch)", x, &r);
ASSERT_RTL_DUMP_EQ_WITH_REUSE ("(reuse_rtx 0)", x, &r);
ASSERT_RTL_DUMP_EQ_WITH_REUSE ("(reuse_rtx 0)", x, &r);
ASSERT_RTL_DUMP_EQ_WITH_REUSE ("(1|scratch)", y, &r);
ASSERT_RTL_DUMP_EQ_WITH_REUSE ("(reuse_rtx 1)", y, &r);
ASSERT_RTL_DUMP_EQ_WITH_REUSE ("(reuse_rtx 1)", y, &r);
/* z only appears once and thus shouldn't be prefixed with a
reuse ID. */
ASSERT_RTL_DUMP_EQ_WITH_REUSE ("(scratch)", z, &r);
}
rtx
gen_rtx_fmt_ (RTX_CODE code, enum machine_mode mode)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
return rt;
}
rtx
gen_rtx_fmt_0 (RTX_CODE code, enum machine_mode mode)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
X0EXP (rt, 0) = NULL_RTX;
return rt;
}
rtx
gen_rtx_fmt_w (RTX_CODE code, enum machine_mode mode,
HOST_WIDE_INT arg0)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XWINT (rt, 0) = arg0;
return rt;
}
rtx
gen_rtx_fmt_s (RTX_CODE code, enum machine_mode mode,
const char *arg0)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XSTR (rt, 0) = arg0;
return rt;
}
rtx
gen_rtx_fmt_i (RTX_CODE code, enum machine_mode mode,
int arg0)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XINT (rt, 0) = arg0;
return rt;
}
rtx
gen_rtx_fmt_e (RTX_CODE code, enum machine_mode mode,
rtx arg0)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XEXP (rt, 0) = arg0;
return rt;
}
rtx
gen_rtx_fmt_i00 (RTX_CODE code, enum machine_mode mode,
int arg0)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XINT (rt, 0) = arg0;
X0EXP (rt, 1) = NULL_RTX;
X0EXP (rt, 2) = NULL_RTX;
return rt;
}
rtx
gen_rtx_fmt_te (RTX_CODE code, enum machine_mode mode,
union tree_node *arg0,
rtx arg1)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XTREE (rt, 0) = arg0;
XEXP (rt, 1) = arg1;
return rt;
}
rtx
gen_rtx_fmt_is (RTX_CODE code, enum machine_mode mode,
int arg0,
const char *arg1)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XINT (rt, 0) = arg0;
XSTR (rt, 1) = arg1;
return rt;
}
rtx
gen_rtx_fmt_sE (RTX_CODE code, enum machine_mode mode,
const char *arg0,
rtvec arg1)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XSTR (rt, 0) = arg0;
XVEC (rt, 1) = arg1;
return rt;
}
rtx
gen_rtx_fmt_Ee (RTX_CODE code, enum machine_mode mode,
rtvec arg0,
rtx arg1)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XVEC (rt, 0) = arg0;
XEXP (rt, 1) = arg1;
return rt;
}
rtx
gen_rtx_fmt_s00 (RTX_CODE code, enum machine_mode mode,
const char *arg0)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XSTR (rt, 0) = arg0;
X0EXP (rt, 1) = NULL_RTX;
X0EXP (rt, 2) = NULL_RTX;
return rt;
}
rtx
gen_rtx_fmt_ei (RTX_CODE code, enum machine_mode mode,
rtx arg0,
int arg1)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XEXP (rt, 0) = arg0;
XINT (rt, 1) = arg1;
return rt;
}
static void
test_dumping_insns ()
{
/* Barriers. */
rtx_barrier *barrier = as_a <rtx_barrier *> (rtx_alloc (BARRIER));
SET_NEXT_INSN (barrier) = NULL;
ASSERT_RTL_DUMP_EQ ("(cbarrier 0)\n", barrier);
/* Labels. */
rtx_insn *label = gen_label_rtx ();
CODE_LABEL_NUMBER (label) = 42;
ASSERT_RTL_DUMP_EQ ("(clabel 0 42)\n", label);
LABEL_NAME (label)= "some_label";
ASSERT_RTL_DUMP_EQ ("(clabel 0 42 (\"some_label\"))\n", label);
}
rtx
gen_rtx_fmt_sse (RTX_CODE code, enum machine_mode mode,
const char *arg0,
const char *arg1,
rtx arg2)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XSTR (rt, 0) = arg0;
XSTR (rt, 1) = arg1;
XEXP (rt, 2) = arg2;
return rt;
}
rtx
gen_rtx_fmt_sies (RTX_CODE code, enum machine_mode mode,
const char *arg0,
int arg1,
rtx arg2,
const char *arg3)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XSTR (rt, 0) = arg0;
XINT (rt, 1) = arg1;
XEXP (rt, 2) = arg2;
XSTR (rt, 3) = arg3;
return rt;
}
rtx
gen_rtx_fmt_eEee0 (RTX_CODE code, enum machine_mode mode,
rtx arg0,
rtvec arg1,
rtx arg2,
rtx arg3)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XEXP (rt, 0) = arg0;
XVEC (rt, 1) = arg1;
XEXP (rt, 2) = arg2;
XEXP (rt, 3) = arg3;
X0EXP (rt, 4) = NULL_RTX;
return rt;
}
rtx
gen_rtx_fmt_iuu000000 (RTX_CODE code, enum machine_mode mode,
int arg0,
rtx arg1,
rtx arg2)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XINT (rt, 0) = arg0;
XEXP (rt, 1) = arg1;
XEXP (rt, 2) = arg2;
X0EXP (rt, 3) = NULL_RTX;
X0EXP (rt, 4) = NULL_RTX;
X0EXP (rt, 5) = NULL_RTX;
X0EXP (rt, 6) = NULL_RTX;
X0EXP (rt, 7) = NULL_RTX;
X0EXP (rt, 8) = NULL_RTX;
return rt;
}
rtx
gen_rtx_fmt_iuuB00is (RTX_CODE code, enum machine_mode mode,
int arg0,
rtx arg1,
rtx arg2,
struct basic_block_def *arg3,
int arg4,
const char *arg5)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XINT (rt, 0) = arg0;
XEXP (rt, 1) = arg1;
XEXP (rt, 2) = arg2;
XBBDEF (rt, 3) = arg3;
X0EXP (rt, 4) = NULL_RTX;
X0EXP (rt, 5) = NULL_RTX;
XINT (rt, 6) = arg4;
XSTR (rt, 7) = arg5;
return rt;
}
rtx
gen_rtx_fmt_ssiEEsi (RTX_CODE code, enum machine_mode mode,
const char *arg0,
const char *arg1,
int arg2,
rtvec arg3,
rtvec arg4,
const char *arg5,
int arg6)
{
rtx rt;
rt = rtx_alloc (code);
PUT_MODE (rt, mode);
XSTR (rt, 0) = arg0;
XSTR (rt, 1) = arg1;
XINT (rt, 2) = arg2;
XVEC (rt, 3) = arg3;
XVEC (rt, 4) = arg4;
XSTR (rt, 5) = arg5;
XINT (rt, 6) = arg6;
return rt;
}
static void
process_rtx (rtx desc, int lineno)
{
switch (GET_CODE (desc))
{
case DEFINE_INSN:
queue_pattern (desc, &define_insn_tail, read_rtx_filename, lineno);
break;
case DEFINE_COND_EXEC:
queue_pattern (desc, &define_cond_exec_tail, read_rtx_filename, lineno);
break;
case DEFINE_ATTR:
queue_pattern (desc, &define_attr_tail, read_rtx_filename, lineno);
break;
case INCLUDE:
process_include (desc, lineno);
break;
case DEFINE_INSN_AND_SPLIT:
{
const char *split_cond;
rtx split;
rtvec attr;
int i;
/* Create a split with values from the insn_and_split. */
split = rtx_alloc (DEFINE_SPLIT);
i = XVECLEN (desc, 1);
XVEC (split, 0) = rtvec_alloc (i);
while (--i >= 0)
{
XVECEXP (split, 0, i) = copy_rtx (XVECEXP (desc, 1, i));
remove_constraints (XVECEXP (split, 0, i));
}
/* If the split condition starts with "&&", append it to the
insn condition to create the new split condition. */
split_cond = XSTR (desc, 4);
if (split_cond[0] == '&' && split_cond[1] == '&')
split_cond = concat (XSTR (desc, 2), split_cond, NULL);
XSTR (split, 1) = split_cond;
XVEC (split, 2) = XVEC (desc, 5);
XSTR (split, 3) = XSTR (desc, 6);
/* Fix up the DEFINE_INSN. */
attr = XVEC (desc, 7);
PUT_CODE (desc, DEFINE_INSN);
XVEC (desc, 4) = attr;
/* Queue them. */
queue_pattern (desc, &define_insn_tail, read_rtx_filename, lineno);
queue_pattern (split, &other_tail, read_rtx_filename, lineno);
break;
}
default:
queue_pattern (desc, &other_tail, read_rtx_filename, lineno);
break;
}
}
static void
process_rtx (rtx desc, int lineno)
{
switch (GET_CODE (desc))
{
case DEFINE_INSN:
queue_pattern (desc, &define_insn_tail, read_rtx_filename, lineno);
break;
case DEFINE_COND_EXEC:
queue_pattern (desc, &define_cond_exec_tail, read_rtx_filename, lineno);
break;
case DEFINE_ATTR:
queue_pattern (desc, &define_attr_tail, read_rtx_filename, lineno);
break;
case DEFINE_PREDICATE:
case DEFINE_SPECIAL_PREDICATE:
case DEFINE_CONSTRAINT:
case DEFINE_REGISTER_CONSTRAINT:
case DEFINE_MEMORY_CONSTRAINT:
case DEFINE_ADDRESS_CONSTRAINT:
queue_pattern (desc, &define_pred_tail, read_rtx_filename, lineno);
break;
case INCLUDE:
process_include (desc, lineno);
break;
case DEFINE_INSN_AND_SPLIT:
{
const char *split_cond;
rtx split;
rtvec attr;
int i;
struct queue_elem *insn_elem;
struct queue_elem *split_elem;
/* Create a split with values from the insn_and_split. */
split = rtx_alloc (DEFINE_SPLIT);
i = XVECLEN (desc, 1);
XVEC (split, 0) = rtvec_alloc (i);
while (--i >= 0)
{
XVECEXP (split, 0, i) = copy_rtx (XVECEXP (desc, 1, i));
remove_constraints (XVECEXP (split, 0, i));
}
/* If the split condition starts with "&&", append it to the
insn condition to create the new split condition. */
split_cond = XSTR (desc, 4);
if (split_cond[0] == '&' && split_cond[1] == '&')
{
copy_rtx_ptr_loc (split_cond + 2, split_cond);
split_cond = join_c_conditions (XSTR (desc, 2), split_cond + 2);
}
XSTR (split, 1) = split_cond;
XVEC (split, 2) = XVEC (desc, 5);
XSTR (split, 3) = XSTR (desc, 6);
/* Fix up the DEFINE_INSN. */
attr = XVEC (desc, 7);
PUT_CODE (desc, DEFINE_INSN);
XVEC (desc, 4) = attr;
/* Queue them. */
insn_elem
= queue_pattern (desc, &define_insn_tail, read_rtx_filename,
lineno);
split_elem
= queue_pattern (split, &other_tail, read_rtx_filename, lineno);
insn_elem->split = split_elem;
break;
}
default:
queue_pattern (desc, &other_tail, read_rtx_filename, lineno);
break;
}
}
