void __init s3c2410_init_clocks(int xtal)
{
unsigned long tmp;
unsigned long fclk;
unsigned long hclk;
unsigned long pclk;
/* now we've got our machine bits initialised, work out what
* clocks we've got */
fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
tmp = __raw_readl(S3C2410_CLKDIVN);
/* work out clock scalings */
hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
/* print brieft summary of clocks, etc */
printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
/* initialise the clocks here, to allow other things like the
* console to use them
*/
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
s3c2410_baseclk_add();
}
void __init s3c2410_map_io(struct map_desc *mach_desc, int size)
{
unsigned long tmp;
/* register our io-tables */
iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
iotable_init(mach_desc, size);
/* now we've got our machine bits initialised, work out what
* clocks we've got */
s3c2410_fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), 12*MHZ);
tmp = __raw_readl(S3C2410_CLKDIVN);
//printk("tmp=%08x, fclk=%d\n", tmp, s3c2410_fclk);
/* work out clock scalings */
s3c2410_hclk = s3c2410_fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
s3c2410_pclk = s3c2410_hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
/* print brieft summary of clocks, etc */
printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
print_mhz(s3c2410_fclk), print_mhz(s3c2410_hclk),
print_mhz(s3c2410_pclk));
}
void __init s3c2412_init_clocks(int xtal)
{
unsigned long clkdiv;
unsigned long hclk, fclk, pclk;
int hdiv = 1;
/* now we've got our machine bits initialised, work out what
* clocks we've got */
fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
clkdiv = __raw_readl(S3C2410_CLKDIVN);
/* work out clock scalings */
switch (clkdiv & S3C2412_CLKDIVN_HCLKDIV_MASK) {
case S3C2412_CLKDIVN_HCLKDIV_1_2:
hdiv = 1;
break;
case S3C2412_CLKDIVN_HCLKDIV_2_4:
hdiv = 2;
break;
case S3C2412_CLKDIVN_HCLKDIV_3_6:
hdiv = 3;
break;
case S3C2412_CLKDIVN_HCLKDIV_4_8:
hdiv = 4;
break;
}
if (!(clkdiv & S3C2412_CLKDIVN_ARMDIV))
fclk *= 2;
hclk = fclk / hdiv;
pclk = hclk / ((clkdiv & S3C2412_CLKDIVN_PCLKDIV)? 2 : 1);
if (clkdiv & S3C2412_CLKDIVN_DVSEN)
fclk = hclk;
/* print brief summary of clocks, etc */
printk("S3C2412: core %lu.%03lu MHz, memory %lu.%03lu MHz, peripheral %lu.%03lu MHz\n",
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
/* initialise the clocks here, to allow other things like the
* console to use them, and to add new ones after the initialisation
*/
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
#if defined CONFIG_CPU_FREQ && defined CONFIG_S3C24XX_DFS_CPUFREQ
/* Setup the uartclk. Needs to be done this early so the console can use it. */
s3c2412_setup_uart_clk( xtal );
#endif
}
void __init s3c244x_init_clocks(int xtal)
{
unsigned long clkdiv;
unsigned long camdiv;
unsigned long hclk, fclk, pclk;
int hdiv = 1;
/* now we've got our machine bits initialised, work out what
* clocks we've got */
fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
clkdiv = __raw_readl(S3C2410_CLKDIVN);
camdiv = __raw_readl(S3C2440_CAMDIVN);
/* work out clock scalings */
switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
case S3C2440_CLKDIVN_HDIVN_1:
hdiv = 1;
break;
case S3C2440_CLKDIVN_HDIVN_2:
hdiv = 2;
break;
case S3C2440_CLKDIVN_HDIVN_4_8:
hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
break;
case S3C2440_CLKDIVN_HDIVN_3_6:
hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
break;
}
hclk = fclk / hdiv;
pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);
/* print brief summary of clocks, etc */
printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
/* initialise the clocks here, to allow other things like the
* console to use them, and to add new ones after the initialisation
*/
s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
s3c2410_baseclk_add();
}
static int s3c2440_clk_add(struct sys_device *sysdev)
{
struct clk *clk_xtal;
struct clk *clk_h;
struct clk *clk_p;
int i;
struct clk *clkp;
clk_xtal = clk_get(NULL, "xtal");
if (IS_ERR(clk_xtal)) {
printk(KERN_ERR "S3C2440: Failed to get clk_xtal\n");
return -EINVAL;
}
s3c2440_clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), clk_xtal->rate);
printk("S3C2440: Clock Support, UPLL %lu.%03lu MHz\n",
print_mhz(s3c2440_clk_upll.rate));
clk_h = clk_get(NULL, "hclk");
clk_p = clk_get(NULL, "pclk");
if (IS_ERR(clk_h) || IS_ERR(clk_p)) {
printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
return -EINVAL;
}
s3c24xx_register_clock(&s3c2440_clk_upll);
for (i = 0; i < ARRAY_SIZE(s3c2440_init_clocks); ++i) {
clkp = &s3c2440_init_clocks[i];
switch ((int)clkp->parent) {
case (int)CLK_H:
clkp->parent = clk_h;
break;
case (int)CLK_P:
clkp->parent = clk_p;
break;
default:
clkp->parent = NULL;
break;
}
s3c24xx_register_clock(clkp);
}
return 0;
}
static int s3c2440_clk_add(struct sys_device *sysdev)
{
unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
struct clk *clk_h;
struct clk *clk_p;
struct clk *clk_xtal;
clk_xtal = clk_get(NULL, "xtal");
if (IS_ERR(clk_xtal)) {
printk(KERN_ERR "S3C2440: Failed to get clk_xtal\n");
return -EINVAL;
}
s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate);
printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n",
print_mhz(s3c2440_clk_upll.rate));
clk_p = clk_get(NULL, "pclk");
clk_h = clk_get(NULL, "hclk");
if (IS_ERR(clk_p) || IS_ERR(clk_h)) {
printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
return -EINVAL;
}
s3c2440_clk_cam.parent = clk_h;
s3c2440_clk_ac97.parent = clk_p;
s3c24xx_register_clock(&s3c2440_clk_ac97);
s3c24xx_register_clock(&s3c2440_clk_cam);
s3c24xx_register_clock(&s3c2440_clk_upll);
clk_disable(&s3c2440_clk_ac97);
clk_disable(&s3c2440_clk_cam);
return 0;
}
