/**
* This function reset rtc
*/
void rt_hw_rtc_reset (void)
{
register rt_uint32_t regv;
regv = s3c_readl(RTCCON);
regv &= ~0x06;
regv |= 0x08;
s3c_writel(regv, RTCCON);
regv = s3c_readl(RTCCON);
regv &= ~(0x08|0x01);
s3c_writel(regv, RTCCON);
}
int serial_init(int baudrate)
{
unsigned int regv;
// UART I/O port initialize (RXD0 : GPA0, TXD0: GPA1)
regv = s3c_readl(GPACON);
regv = (regv & ~(0xff<<0)) | (0x22<<0); // GPA0->RXD0, GPA1->TXD0
s3c_writel(regv, GPACON);
regv = s3c_readl(GPAPUD);
regv = (regv & ~(0xf<<0)) | (0x1<<0); // RXD0: Pull-down, TXD0: pull up/down disable
s3c_writel(regv, GPAPUD);
/// Normal Mode, No Parity, 1 Stop Bit, 8 Bit Data
s3c_writel(0x0003, ULCON0);
// PCLK divide, Polling Mode
regv = (1<<9) | (1<<8) | (1<<2) | (1<<0);
s3c_writel(regv, UCON0);
// Disable FIFO
s3c_writel(0x0000, UFCON0);
// Disable Auto Flow Control
s3c_writel(0x0000, UMCON0);
// Baud rate, DIV=PCLK/(BPS*16)-1; 66000000/(115200*16)-1 = 34;
s3c_writel(34, UBRDIV0);
for (regv=0; regv<0x100; regv++);
//aSlotTable[DivSlot];
s3c_writel(0x80, UDIVSLOT0);
return 0;
}
static void
s3c24xxShutdownDMA(volatile uint32 *channels)
{
int dma_ch;
volatile uint32 *ch;
uint32 dmasktrig;
int timeo;
for (dma_ch = 0; dma_ch < 4; dma_ch++) {
ch = channels + ((0x40 / 4) * dma_ch);
dmasktrig = s3c_readl(ch, S3C2410_DMA_DMASKTRIG);
if (dmasktrig & S3C2410_DMASKTRIG_ON) {
s3c_writel(ch, S3C2410_DMA_DMASKTRIG, S3C2410_DMASKTRIG_STOP);
timeo = 0x100000;
while (timeo > 0) {
dmasktrig = s3c_readl(ch, S3C2410_DMA_DMASKTRIG);
if ((dmasktrig & S3C2410_DMASKTRIG_ON) == 0)
break;
if (timeo-- <= 0)
break;
}
}
}
}
/**
* This function set rtc time
*/
void rt_hw_rtc_set(struct tm *ti)
{
rt_uint8_t sec, min, hour, mday, wday, mon, year;
year = BIN2BCD(ti->tm_year);
mon = BIN2BCD(ti->tm_mon);
wday = BIN2BCD(ti->tm_wday);
mday = BIN2BCD(ti->tm_mday);
hour = BIN2BCD(ti->tm_hour);
min = BIN2BCD(ti->tm_min);
sec = BIN2BCD(ti->tm_sec);
/* enable access to RTC registers */
RTC_ENABLE();
do{
/* write RTC registers */
s3c_writel(sec, BCDSEC);
s3c_writel(min, BCDMIN);
s3c_writel(hour, BCDHOUR);
s3c_writel(mday, BCDDATE);
s3c_writel(wday, BCDDAY);
s3c_writel(mon, BCDMON);
s3c_writel(year, BCDYEAR);
}while (sec != s3c_readl(BCDSEC));
/* disable access to RTC registers */
RTC_DISABLE();
}
void serial_putc(const char ch)
{
/* wait for room in the tx FIFO */
while (!(s3c_readl(UTRSTAT0) & 0x2));
s3c_writel(ch, UTXH0);
/* If \n, also do \r */
if (ch == '\n')
serial_putc('\r');
}
void
MachineS3c6400::s3c6400ShutdownDMA(struct fbinfo *fbi)
{
volatile uint32 * SDMA_SEL;
volatile uint32 * DMA_CTRL;
uint32 ch_conf, config;
int timeout;
int dma_ctrl, dma_ch, sdma_sel;
int ctrl_count=4;
const uint32 S3C6410_DMA_CTRL_LIST[] =
{ S3C6400_PA_DMA0, S3C6400_PA_DMA1, S3C6400_PA_SDMA0, S3C6400_PA_SDMA1 };
SDMA_SEL = (uint32*)memPhysMap(0x7E00F110);
if (SDMA_SEL) {
sdma_sel = SDMA_SEL[0];
fb_printf(fbi,"%s: SDMA_SEL=%x", __func__, sdma_sel);
if (sdma_sel == 0xcfffffff)
//SDMA disabled
ctrl_count = 2;
//set to standard DMA
SDMA_SEL[0]=0xcfffffff;
}
fb_printf(fbi, " set\n");
/* 6410 : we have 2 (+2 secure) controllers with 8 channels each */
for (dma_ctrl = 0; dma_ctrl < ctrl_count; dma_ctrl++) {
DMA_CTRL = (uint32*) memPhysMap(S3C6410_DMA_CTRL_LIST[dma_ctrl]);
if (DMA_CTRL) {
config = s3c_readl(DMA_CTRL, PL080_EN_CHAN);
if (config == 0) {
fb_printf(fbi, "%s: controller %d already disabled\n", __func__, dma_ctrl);
fb_printf(fbi, "%s: clear controller %d irq\n", __func__, dma_ctrl);
s3c_writel(DMA_CTRL, PL080_TC_CLEAR, 0xFF);
s3c_writel(DMA_CTRL, PL080_ERR_CLEAR, 0xFF);
fb_printf(fbi, "%s: clear controller %d irq done\n", __func__, dma_ctrl);
//continue;
}
for (dma_ch = 0; dma_ch < 8; dma_ch ++) {
int offset = 0x114 + (dma_ch*0x20);
//if (dma_ctrl < 2)
// ch_conf = PL080_Cx_CONFIG(dma_ch);
//else
ch_conf = PL080S_Cx_CONFIG(dma_ch);
config = s3c_readl(DMA_CTRL, ch_conf);
config |= PL080_CONFIG_HALT;
s3c_writel(DMA_CTRL, ch_conf, config);
timeout = 1000;
do {
config = s3c_readl(DMA_CTRL, ch_conf);
fb_printf(fbi, "%s: dma_ctrl %d, dma_ch %d : t%d - config@%x/%x = %x\n", __func__, dma_ctrl, dma_ch, timeout, ch_conf, offset, config);
if (config & PL080_CONFIG_ACTIVE)
s3c_udelay(10);
else
break;
} while (--timeout > 0);
if (config & PL080_CONFIG_ACTIVE) {
fb_printf(fbi, "%s: channel still active\n", __func__);
// return -EFAULT;
}
config = s3c_readl(DMA_CTRL, ch_conf);
config &= ~PL080_CONFIG_ENABLE;
s3c_writel(DMA_CTRL, ch_conf, config);
}
}
/* clear controller interrupts */
fb_printf(fbi, "%s: clear controller %d irq\n", __func__, dma_ctrl);
s3c_writel(DMA_CTRL, PL080_TC_CLEAR, 0xFF);
s3c_writel(DMA_CTRL, PL080_ERR_CLEAR, 0xFF);
fb_printf(fbi, "%s: clear controller %d irq done\n", __func__, dma_ctrl);
}
fb_printf(fbi, "%s: done\n", __func__);
return;
}
static inline void RTC_DISABLE(void)
{
s3c_writel(s3c_readl(RTCCON) & ~0x01, RTCCON); /* RTC read and write disable */
}
static inline void RTC_ENABLE(void)
{
s3c_writel(s3c_readl(RTCCON) | 0x01, RTCCON); /*RTC read and write enable */
}
