static bool wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit,
u32 status)
{
unsigned long timeout = jiffies + usecs_to_jiffies(1000);
while (time_before(jiffies, timeout)) {
if (sata_is_reg(base, reg, checkbit, status))
return true;
}
return false;
}
static bool wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit,
u32 status)
{
u16 time_limit_cnt = 0;
while (!sata_is_reg(base, reg, checkbit, status)) {
if (time_limit_cnt == SATA_TIME_LIMIT)
return false;
udelay(1000);
time_limit_cnt++;
}
return true;
}
static bool wait_for_reg_status(void __iomem *base, u32 reg, u32 checkbit,
u32 Status)
{
time_limit_cnt = 0;
while (!sata_is_reg(base, reg, checkbit, Status)) {
if (time_limit_cnt == SATA_TIME_LIMIT) {
printk(KERN_ERR " Register Status wait FAIL\n");
return false;
}
udelay(1000);
time_limit_cnt++;
}
return true;
}
static int exynos_sataphy_init(struct sata_phy *phy)
{
int ret;
u32 val;
/* Values to be written to enable 40 bits interface */
u8 buf[] = { 0x3A, 0x0B };
struct exynos_sata_phy *sata_phy;
if (!i2c_client)
return -EPROBE_DEFER;
sata_phy = container_of(phy, struct exynos_sata_phy, phy);
ret = clk_prepare_enable(sata_phy->clk);
if (ret < 0) {
dev_err(phy->dev, "failed to enable source clk\n");
return ret;
}
if (sata_is_reg(sata_phy->mmio , EXYNOS5_SATA_CTRL0,
CTRL0_P0_PHY_CALIBRATED, CTRL0_P0_PHY_CALIBRATED))
return 0;
writel(SATA_PHY_PMU_EN, sata_phy->pmureg);
val = 0;
writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
val |= 0xFF;
writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
val |= LINK_RESET;
writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
val |= RESET_CMN_RST_N;
writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
val = readl(sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
val &= ~PHCTRLM_REF_RATE;
writel(val, sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
/* High speed enable for Gen3 */
val = readl(sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
val |= PHCTRLM_HIGH_SPEED;
writel(val, sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
val = readl(sata_phy->mmio + EXYNOS5_SATA_CTRL0);
val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;
writel(val, sata_phy->mmio + EXYNOS5_SATA_CTRL0);
writel(0x2, sata_phy->mmio + EXYNOS5_SATA_MODE0);
ret = i2c_master_send(i2c_client, buf, sizeof(buf));
if (ret < 0)
return -ENXIO;
/* release cmu reset */
val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
val &= ~RESET_CMN_RST_N;
writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
val |= RESET_CMN_RST_N;
writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
if (wait_for_reg_status(sata_phy->mmio, EXYNOS5_SATA_PHSATA_STATM,
PHSTATM_PLL_LOCKED, 1)) {
return 0;
}
return -EINVAL;
}
static int sataphy_init(struct sata_phy *phy)
{
int ret;
u32 val;
/* Values to be written to enable 40 bits interface */
u8 buf[] = { 0x3A, 0x0B };
struct exynos_sata_phy *sata_phy;
if (!i2c_client)
return -EPROBE_DEFER;
sata_phy = (struct exynos_sata_phy *)phy->priv_data;
clk_enable(sata_phy->clk);
if (sata_is_reg(sata_phy->mmio , EXYNOS5_SATA_CTRL0,
CTRL0_P0_PHY_CALIBRATED, CTRL0_P0_PHY_CALIBRATED))
return 0;
writel(S5P_PMU_SATA_PHY_CONTROL_EN, EXYNOS5_SATA_PHY_CONTROL);
val = 0;
writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
val |= 0xFF;
writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
val |= LINK_RESET;
writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
val |= RESET_CMN_RST_N;
writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
val = readl(sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
val &= ~PHCTRLM_REF_RATE;
writel(val, sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
/* High speed enable for Gen3 */
val = readl(sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
val |= PHCTRLM_HIGH_SPEED;
writel(val, sata_phy->mmio + EXYNOS5_SATA_PHSATA_CTRLM);
val = readl(sata_phy->mmio + EXYNOS5_SATA_CTRL0);
val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;
writel(val, sata_phy->mmio + EXYNOS5_SATA_CTRL0);
writel(SATA_PHY_GENERATION3, sata_phy->mmio + EXYNOS5_SATA_MODE0);
ret = i2c_master_send(i2c_client, buf, sizeof(buf));
if (ret < 0)
return -EINVAL;
/* release cmu reset */
val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
val &= ~RESET_CMN_RST_N;
writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
val = readl(sata_phy->mmio + EXYNOS5_SATA_RESET);
val |= RESET_CMN_RST_N;
writel(val, sata_phy->mmio + EXYNOS5_SATA_RESET);
if (wait_for_reg_status(sata_phy->mmio, EXYNOS5_SATA_PHSATA_STATM,
PHSTATM_PLL_LOCKED, 1)) {
return 0;
}
return -EINVAL;
}
