static void saturn_instruction_80(saturn_state *cpustate)
{
int op;
switch(READ_OP(cpustate)) {
case 0: saturn_out_cs(cpustate);break;
case 1: saturn_out_c(cpustate);break;
case 2: saturn_in(cpustate, A);break;
case 3: saturn_in(cpustate, C);break;
case 4: saturn_mem_unconfig(cpustate);break;
case 5: saturn_mem_config(cpustate);break;
case 6: saturn_mem_id(cpustate);break;
case 7: saturn_shutdown(cpustate);break;
case 8:
switch(READ_OP(cpustate)) {
case 0: saturn_interrupt_on(cpustate);break;
case 1:
switch(op=READ_OP(cpustate)) {
case 0: saturn_reset_interrupt(cpustate);break;
default: saturn_invalid5( cpustate, 8, 0, 8, 1, op ); break;
}
break;
case 2: saturn_load_reg(cpustate, A);break; //la
case 3: saturn_bus_command_b(cpustate);break;
case 4: saturn_clear_bit(cpustate, A);break; // abit=0
case 5: saturn_set_bit(cpustate, A);break; // abit=1
case 6: saturn_jump_bit_clear(cpustate, A);break;
case 7: saturn_jump_bit_set(cpustate, A);break;
case 8: saturn_clear_bit(cpustate, C);break; // cbit=0
case 9: saturn_set_bit(cpustate, C);break; // cbit=1
case 0xa: saturn_jump_bit_clear(cpustate, C);break;
case 0xb: saturn_jump_bit_set(cpustate, C);break;
case 0xc: saturn_indirect_jump(cpustate, A);break;
case 0xd: saturn_bus_command_d(cpustate);break;
case 0xe: saturn_indirect_jump(cpustate, C);break;
case 0xf: saturn_interrupt_off(cpustate);break;
}
break;
case 9: saturn_ca_p_1(cpustate);break;//C+P+1
case 0xa: saturn_mem_reset(cpustate);break;
case 0xb: saturn_bus_command_b(cpustate);break;
case 0xc: saturn_p_to_c(cpustate);break;
case 0xd: saturn_c_to_p(cpustate);break;
case 0xe: saturn_serial_request(cpustate);break;
case 0xf: saturn_exchange_p(cpustate);break;
}
}
static void saturn_instruction_80(void)
{
switch(READ_OP()) {
case 0: saturn_out_cs();break;
case 1: saturn_out_c();break;
case 2: saturn_in(A);break;
case 3: saturn_in(C);break;
case 4: saturn_mem_unconfig();break;
case 5: saturn_mem_config();break;
case 6: saturn_mem_id();break;
case 7: saturn_shutdown();break;
case 8:
switch(READ_OP()) {
case 0: saturn_interrupt_on();break;
case 1:
switch(READ_OP()) {
case 0: saturn_reset_interrupt();break;
}
break;
case 2: saturn_load_reg(A);break; /*la */
case 3: saturn_bus_command_c();break;
case 4: saturn_clear_bit(A);break; /* abit=0 */
case 5: saturn_set_bit(A);break; /* abit=1 */
case 6: saturn_jump_bit_clear(A);break;
case 7: saturn_jump_bit_set(A);break;
case 8: saturn_clear_bit(C);break; /* cbit=0 */
case 9: saturn_set_bit(C);break; /* cbit=1 */
case 0xa: saturn_jump_bit_clear(C);break;
case 0xb: saturn_jump_bit_set(C);break;
case 0xc: saturn_indirect_jump(A);break;
case 0xd: saturn_bus_command_d();break;
case 0xe: saturn_indirect_jump(C);break;
case 0xf: saturn_interrupt_off();break;
}
break;
case 9: saturn_ca_p_1();break;/*C+P+1 */
case 0xa: saturn_mem_reset();break;
case 0xb: saturn_bus_command_b();break;
case 0xc: saturn_p_to_c();break;
case 0xd: saturn_c_to_p();break;
case 0xe: saturn_serial_request();break;
case 0xf: saturn_exchange_p();break;
}
}