void omap3_restore_core_settings(void)
{
prcm_lock_iva_dpll(prcm_get_current_vdd1_opp());
restore_sram_functions();
omap_sram_idle_setup();
save_scratchpad_contents();
}
int __init omap3_pm_init(void)
{
int ret;
printk(KERN_ERR "OMAP 3430 Power Management subsystem initializing.\n");
omap_sram_idle_setup();
suspend_set_ops(&omap_pm_ops);
/* In case of cold boot, clear scratchpad */
if (RM_RSTST_CORE & 0x1)
clear_scratchpad_contents();
#ifdef CONFIG_MPU_OFF
save_scratchpad_contents();
#endif
/*
* Initialize the PRCM subsystem
*/
prcm_init();
memret1 = (struct res_handle *)resource_get("resouret1", "core_mem1ret");
memret2 = (struct res_handle *)resource_get("resouret12", "core_mem2ret");
logret1 = (struct res_handle *)resource_get("logic retntion", "core_logicret");
/* Initialize settings for voltage scaling.
*/
if (0 != prcm_vdd_clk_init()) {
printk(KERN_ERR "could not initialize clocks.\n");
return -1;
}
PRM_IRQSTATUS_MPU = 0x3FFFFFD; // It takes into account reserved bits
PRM_IRQENABLE_MPU = 0x201; // IOPAD + WKUP event
#ifdef CONFIG_OMAP_VOLT_SR_BYPASS
/* Enabling the VOLTAGE CONTROLLER PRCM interrupts */
PRM_IRQENABLE_MPU |= PRM_VC_TIMEOUTERR_EN | PRM_VC_RAERR_EN|
PRM_VC_SAERR_EN;
#endif /* #ifdef CONFIG_OMAP_VOLT_SR_BYPASS */
/* Registering PRCM Interrupts to MPU, for Wakeup events */
ret = request_irq(PRCM_MPU_IRQ, prcm_interrupt_handler,
IRQF_DISABLED, "prcm", NULL);
if (ret) {
printk(KERN_ERR "request_irq failed to register for 0x%x\n",
PRCM_MPU_IRQ);
return -1;
}
#ifdef CONFIG_PROC_FS
create_pmproc_entry();
#endif
return 0;
}
static int omap3_select_table_rate(struct clk *clk, unsigned long rate)
{
u8 cpu_mask = 0;
u32 cur_vdd_rate, current_opp;
struct vdd_prcm_config *prcm_vdd;
unsigned long found_speed = 0;
int ret = -EINVAL;
int div = 0;
if ((clk != &virt_vdd1_prcm_set) && (clk != &virt_vdd2_prcm_set))
return ret;
if (cpu_is_omap3430())
cpu_mask = RATE_IN_343X;
if (clk == &virt_vdd1_prcm_set)
prcm_vdd = vdd1_rate_table + MAX_VDD1_OPP;
else
prcm_vdd = vdd2_rate_table + MAX_VDD2_OPP;
for (; prcm_vdd->speed; prcm_vdd--) {
if (!(prcm_vdd->flags & cpu_mask))
continue;
if (prcm_vdd->speed <= rate) {
found_speed = prcm_vdd->speed;
pr_debug("Found speed = %lu\n", found_speed);
break;
}
}
if (!found_speed) {
printk(KERN_INFO "Could not set table rate to %luMHz\n",
rate / 1000000);
return -EINVAL;
}
if (clk == &virt_vdd1_prcm_set) {
ret =
prcm_get_processor_speed(clk->parent->prcmid,
&cur_vdd_rate);
if (ret != PRCM_PASS)
return -EINVAL;
current_opp = curr_vdd1_prcm_set->opp;
} else {
ret = prcm_get_dpll_rate(clk->parent->prcmid,
&cur_vdd_rate);
if (ret != PRCM_PASS)
return -EINVAL;
/* Now cur_vdd_rate holds value of core_ck */
/* The divider for l3_ck */
ret = prcm_clksel_get_divider((&l3_ck)->prcmid, &div);
if ((ret != PRCM_PASS) || (div == 0))
return -EINVAL;
cur_vdd_rate /= div;
current_opp = curr_vdd2_prcm_set->opp;
}
cur_vdd_rate *= 1000;
pr_debug("Current rate:%u\n", cur_vdd_rate);
if (cur_vdd_rate != found_speed) {
ret =
prcm_do_frequency_scaling(prcm_vdd->opp,
current_opp);
if (ret != PRCM_PASS)
return -EINVAL;
#ifdef CONFIG_CORE_OFF
save_scratchpad_contents();
#endif
}
if (clk == &virt_vdd1_prcm_set) {
curr_vdd1_prcm_set = prcm_vdd;
omap3_clk_recalc(&mpu_ck);
omap3_propagate_rate(&mpu_ck);
omap3_clk_recalc(&iva2_ck);
omap3_propagate_rate(&iva2_ck);
#ifndef CONFIG_CPU_FREQ
/*Update loops_per_jiffy if processor speed is being changed*/
loops_per_jiffy = compute_lpj(loops_per_jiffy,
(cur_vdd_rate / 1000),
(found_speed / 1000));
#endif
} else {
curr_vdd2_prcm_set = prcm_vdd;
omap3_clk_recalc(&core_ck);
omap3_propagate_rate(&core_ck);
omap3_clk_recalc(&core_x2_ck);
omap3_propagate_rate(&core_x2_ck);
omap3_clk_recalc(&emul_core_alwon_ck);
omap3_propagate_rate(&emul_core_alwon_ck);
}
return 0;
}
static int omap3_enter_idle(struct cpuidle_device *dev,
struct cpuidle_state *state)
{
struct omap3_processor_cx *cx;
struct timespec ts_preidle;
struct timespec ts_postidle;
struct timespec ts_idle;
/* Used for LPR mode DSS context save/restore. */
u32 pm_wken_dss = 0;
u32 pm_pwstctrl_dss = 0;
u32 cm_clkstctrl_dss = 0;
u32 cm_fclken_dss = 0;
u32 cm_iclken_dss = 0;
u32 cm_autoidle_dss = 0;
u32 fclken_core;
u32 iclken_core;
u32 fclken_per;
u32 iclken_per;
int wakeup_latency;
struct system_power_state target_state;
struct system_power_state cur_state;
#ifdef CONFIG_HW_SUP_TRANS
u32 sleepdep_per;
u32 wakedep_per;
#endif /* #ifdef CONFIG_HW_SUP_TRANS */
u32 sdrc_power_register = 0;
int core_sleep_flg = 0;
int got_console_lock = 0;
/* Disable interrupts.
*/
local_irq_disable();
local_fiq_disable();
/* If need resched - return immediately
*/
if( need_resched()) {
local_fiq_enable();
local_irq_enable();
return 0;
}
/* Reset previous power state registers.
*/
clear_prepwstst();
omap3_idle_setup_wkup_sources ();
/* Set up target state from state context provided by cpuidle.
*/
cx = cpuidle_get_statedata(state);
target_state.mpu_state = cx->mpu_state;
target_state.core_state = cx->core_state;
target_state.neon_state = 0; /* Avoid gcc warning. Will be set in
adjust_target_states(). */
/* take a time marker for residency.
*/
getnstimeofday(&ts_preidle);
/* If the requested state is C0, we bail here...
*/
if (cx->type == OMAP3_STATE_C1) {
omap_sram_idle(target_state.mpu_state);
goto return_sleep_time;
}
if (cx->type > OMAP3_STATE_C2)
sched_clock_idle_sleep_event(); /* about to enter deep idle */
/* Adjust PER and NEON domain target states as well as CORE domain
* target state depending on MPU/CORE setting, enable_off sysfs entry
* and PER timer status.
*/
adjust_target_states(&target_state);
wakeup_latency = cx->wakeup_latency;
/* NOTE:
* We will never get the condition below as we are not supporting
* CORE OFF right now. Keeping this code around for future reference.
*/
if (target_state.core_state != cx->core_state) {
/* Currently, this can happen only for core_off. Adjust wakeup
* latency to that of core_cswr state. Hard coded now and needs
* to be made more generic omap3_power_states[4] is CSWR for
* core */
wakeup_latency = omap3_power_states[4].wakeup_latency;
}
/* Reprogram next wake up tick to adjust for wake latency */
if (wakeup_latency > 1000) {
struct tick_device *d = tick_get_device(smp_processor_id());
ktime_t now = ktime_get();
if (ktime_to_ns(ktime_sub(d->evtdev->next_event, now)) >
(wakeup_latency * 1000 + NSEC_PER_MSEC)) {
ktime_t adjust = ktime_set(0, (wakeup_latency * 1000));
ktime_t next = ktime_sub(d->evtdev->next_event, adjust);
clockevents_program_event(d->evtdev, next, now);
}
}
/* Check for pending interrupts. If there is an interrupt, return */
if (INTCPS_PENDING_IRQ0 | INTCPS_PENDING_IRQ1 | INTCPS_PENDING_IRQ2)
goto return_sleep_time;
/* Remember the current power states and clock settings.
*/
prcm_get_power_domain_state(DOM_PER, &cur_state.per_state);
prcm_get_power_domain_state(DOM_CAM, &cur_state.cam_state);
prcm_get_power_domain_state(DOM_SGX, &cur_state.sgx_state);
prcm_get_power_domain_state(DOM_NEON, &cur_state.neon_state);
fclken_core = CM_FCLKEN1_CORE;
iclken_core = CM_ICLKEN1_CORE;
fclken_per = CM_FCLKEN_PER;
iclken_per = CM_ICLKEN_PER;
#ifdef CONFIG_HW_SUP_TRANS
/* Facilitating SWSUP RET, from HWSUP mode */
sleepdep_per = CM_SLEEPDEP_PER;
wakedep_per = PM_WKDEP_PER;
#endif /* #ifdef CONFIG_HW_SUP_TRANS */
/* If target state if core_off, save registers before changing
* anything.
*/
if (target_state.core_state >= PRCM_CORE_OSWR_MEMRET) {
prcm_save_registers();
}
/* Check for pending interrupts. If there is an interrupt, return */
if (INTCPS_PENDING_IRQ0 | INTCPS_PENDING_IRQ1 | INTCPS_PENDING_IRQ2)
goto return_sleep_time;
/* Program MPU and NEON to target state */
if (target_state.mpu_state > PRCM_MPU_ACTIVE) {
if ((cur_state.neon_state == PRCM_ON) &&
(target_state.neon_state != PRCM_ON)) {
if (target_state.neon_state == PRCM_OFF)
omap3_save_neon_context();
prcm_transition_domain_to(DOM_NEON, target_state.neon_state);
}
#ifdef _disabled_CONFIG_MPU_OFF
/* Populate scratchpad restore address */
scratchpad_set_restore_addr();
#endif
/* TODO No support for OFF Mode yet
if(target_state.core_state > PRCM_CORE_CSWR_MEMRET)
omap3_save_secure_ram_context(target_state.core_state);
*/
prcm_set_mpu_domain_state(target_state.mpu_state);
}
/* Check for pending interrupts. If there is an interrupt, return */
if (INTCPS_PENDING_IRQ0 | INTCPS_PENDING_IRQ1 | INTCPS_PENDING_IRQ2)
goto restore;
/* Program CORE and PER to target state */
if (target_state.core_state > PRCM_CORE_ACTIVE) {
/* Log core sleep attempt */
core_sleep_flg = 1;
/* Lock the console to prevent potential access to UARTs.
*/
if (0 == try_acquire_console_sem()) {
got_console_lock = 1;
}
/* Handle PER, CAM and SGX domains. */
if ((cur_state.per_state == PRCM_ON) &&
(target_state.per_state != PRCM_ON)) {
if (target_state.per_state == PRCM_OFF) {
omap3_save_per_context();
}
prcm_transition_domain_to(DOM_PER, target_state.per_state);
}
if (PRCM_ON == cur_state.cam_state)
prcm_transition_domain_to(DOM_CAM, PRCM_RET);
if (PRCM_ON == cur_state.sgx_state)
prcm_transition_domain_to(DOM_SGX, PRCM_RET);
disable_smartreflex(SR1_ID);
disable_smartreflex(SR2_ID);
prcm_set_core_domain_state(target_state.core_state);
/* Enable Autoidle for GPT1 explicitly - Errata 1.4 */
CM_AUTOIDLE_WKUP |= 0x1;
/* Disable HSUSB OTG ICLK explicitly*/
CM_ICLKEN1_CORE &= ~0x10;
/* Enabling GPT1 wake-up capabilities */
PM_WKEN_WKUP |= 0x1;
/* Errata 2.15
* Configure UARTs to ForceIdle. Otherwise they can prevent
* CORE RET.
*/
omap24xx_uart_set_force_idle();
CM_ICLKEN1_CORE &= ~(1<<7); /* MAILBOXES */
CM_ICLKEN1_CORE &= ~(1<<6); /* OMAPCTRL */
/* If we are in LPR mode we need to set up DSS accordingly.
*/
if (omap2_disp_lpr_is_enabled()) {
pm_wken_dss = PM_WKEN_DSS;
pm_pwstctrl_dss = PM_PWSTCTRL_DSS;
cm_clkstctrl_dss = CM_CLKSTCTRL_DSS;
cm_fclken_dss = CM_FCLKEN_DSS;
cm_iclken_dss = CM_ICLKEN_DSS;
cm_autoidle_dss = CM_AUTOIDLE_DSS;
PM_WKEN_DSS = 0x00000001;
PM_PWSTCTRL_DSS = 0x00030107;
CM_CLKSTCTRL_DSS = 0x00000003;
CM_FCLKEN_DSS = 0x00000001;
CM_ICLKEN_DSS = 0x00000001;
CM_AUTOIDLE_DSS = 0x00000001;
}
}
/* Check for pending interrupts. If there is an interrupt, return */
if (INTCPS_PENDING_IRQ0 | INTCPS_PENDING_IRQ1 | INTCPS_PENDING_IRQ2)
goto restore;
#ifdef CONFIG_DISABLE_HFCLK
PRM_CLKSRC_CTRL |= 0x18; /* set sysclk to stop */
#endif /* #ifdef CONFIG_DISABLE_HFCLK */
DEBUG_STATE_CAPTURE();
/* Errata 1.142:
* SDRC not sending auto-refresh when OMAP wakes-up from OFF mode
*/
if (!is_device_type_gp() && is_sil_rev_equal_to(OMAP3430_REV_ES3_0)) {
sdrc_power_register = SDRC_POWER_REG;
SDRC_POWER_REG &= ~(SDRC_PWR_AUTOCOUNT_MASK | SDRC_PWR_CLKCTRL_MASK);
SDRC_POWER_REG |= 0x120;
if (target_state.core_state == PRCM_CORE_OFF)
save_scratchpad_contents();
}
omap_sram_idle(target_state.mpu_state);
/* Errata 1.142:
* SDRC not sending auto-refresh when OMAP wakes-up from OFF mode
*/
if (!is_device_type_gp() && is_sil_rev_equal_to(OMAP3430_REV_ES3_0))
SDRC_POWER_REG = sdrc_power_register;
restore:
#ifdef CONFIG_DISABLE_HFCLK
PRM_CLKSRC_CTRL &= ~0x18;
#endif /* #ifdef CONFIG_DISABLE_HFCLK */
/* Disabling IO_PAD capabilities */
PM_WKEN_WKUP &= ~(0x100);
CM_FCLKEN1_CORE = fclken_core;
CM_ICLKEN1_CORE = iclken_core;
if (target_state.mpu_state > PRCM_MPU_ACTIVE) {
#ifdef _disabled_CONFIG_MPU_OFF
/* On ES 2.0, if scratchpad is populated with valid pointer,
* warm reset does not work So populate scratchpad restore
* address only in cpuidle and suspend calls
*/
scratchpad_clr_restore_addr();
#endif
prcm_set_mpu_domain_state(PRCM_MPU_ACTIVE);
if ((cur_state.neon_state == PRCM_ON) &&
(target_state.mpu_state > PRCM_MPU_INACTIVE)) {
u8 pre_state;
prcm_force_power_domain_state(DOM_NEON, cur_state.neon_state);
prcm_get_pre_power_domain_state(DOM_NEON, &pre_state);
if (pre_state == PRCM_OFF) {
omap3_restore_neon_context();
}
#ifdef CONFIG_HW_SUP_TRANS
prcm_set_power_domain_state(DOM_NEON, POWER_DOMAIN_ON,
PRCM_AUTO);
#endif
}
}
/* Continue core restoration part, only if Core-Sleep is attempted */
if ((target_state.core_state > PRCM_CORE_ACTIVE) && core_sleep_flg) {
u8 pre_per_state;
prcm_set_core_domain_state(PRCM_CORE_ACTIVE);
omap24xx_uart_clr_force_idle();
enable_smartreflex(SR1_ID);
enable_smartreflex(SR2_ID);
/* Turn PER back ON if it was ON before idle.
*/
if (cur_state.per_state == PRCM_ON) {
prcm_force_power_domain_state(DOM_PER, cur_state.per_state);
CM_ICLKEN_PER = iclken_per;
CM_FCLKEN_PER = fclken_per;
prcm_get_pre_power_domain_state(DOM_PER, &pre_per_state);
if (pre_per_state == PRCM_OFF) {
omap3_restore_per_context();
#ifdef CONFIG_OMAP34XX_OFFMODE
context_restore_update(DOM_PER);
#endif
}
#ifdef CONFIG_HW_SUP_TRANS
/* Facilitating SWSUP RET, from HWSUP mode */
CM_SLEEPDEP_PER = sleepdep_per;
PM_WKDEP_PER = wakedep_per;
prcm_set_power_domain_state(DOM_PER, PRCM_ON, PRCM_AUTO);
#endif
}
/* Restore CAM and SGX. */
if (PRCM_ON == cur_state.cam_state)
prcm_transition_domain_to(DOM_CAM, PRCM_ON);
if (PRCM_ON == cur_state.sgx_state)
prcm_transition_domain_to(DOM_SGX, PRCM_ON);
/* If we lost CORE context, restore it.
*/
if (target_state.core_state >= PRCM_CORE_OSWR_MEMRET) {
#ifdef CONFIG_OMAP34XX_OFFMODE
context_restore_update(DOM_CORE1);
#endif
prcm_restore_registers();
prcm_restore_core_context(target_state.core_state);
#ifdef CONFIG_CORE_OFF
omap3_restore_core_settings();
#endif
}
/* Restore DSS settings */
if (omap2_disp_lpr_is_enabled()) {
PM_WKEN_DSS = pm_wken_dss;
PM_PWSTCTRL_DSS = pm_pwstctrl_dss;
CM_CLKSTCTRL_DSS = cm_clkstctrl_dss;
CM_FCLKEN_DSS = cm_fclken_dss;
CM_ICLKEN_DSS = cm_iclken_dss;
CM_AUTOIDLE_DSS = cm_autoidle_dss;
}
/* At this point CORE and PER domain are back. We can release
* the console if we have it.
*/
if (got_console_lock) {
release_console_sem();
}
#ifdef CONFIG_OMAP_32K_TIMER
/* Errata 1.4
* If a General Purpose Timer (GPTimer) is in posted mode
* (TSIRC.POSTED=1), due to internal resynchronizations, values
* read in TCRR, TCAR1 and TCAR2 registers right after the
* timer interface clock (L4) goes from stopped to active may
* not return the expected values. The most common event
* leading to this situation occurs upon wake up from idle.
*
* Software has to wait at least (2 timer interface clock
* cycles + 1 timer functional clock cycle) after L4 clock
* wakeup before reading TCRR, TCAR1 or TCAR2 registers for
* GPTimers in POSTED internal synchro- nization mode, and
* before reading WCRR register of the Watchdog timers . The
* same workaround must be applied before reading CR and
* 32KSYNCNT_REV registers of the synctimer module.
*
* Wait Period = 2 timer interface clock cycles +
* 1 timer functional clock cycle
* Interface clock = L4 clock (50MHz worst case).
* Functional clock = 32KHz
* Wait Period = 2*10^-6/50 + 1/32768 = 0.000030557 = 30.557us
* Rounding off the delay value to a safer 50us.
*/
udelay(GPTIMER_WAIT_DELAY);
#endif
/* Disable autoidling of GPT1.
*/
CM_AUTOIDLE_WKUP &= ~(0x1);
}
DPRINTK("MPU state:%x, CORE state:%x\n",
PM_PREPWSTST_MPU, PM_PREPWSTST_CORE);
/* Do wakeup event check s*/
post_uart_activity();
/* Update stats for sysfs entries.
*/
store_prepwst();
return_sleep_time:
getnstimeofday(&ts_postidle);
#if defined(CONFIG_SYSFS) && defined(DEBUG_BAIL_STATS)
ts_last_wake_up = ts_postidle;
#endif
ts_idle = timespec_sub(ts_postidle, ts_preidle);
if (cx->type > OMAP3_STATE_C2)
sched_clock_idle_wakeup_event(timespec_to_ns(&ts_idle));
DEBUG_STATE_PRINT(core_sleep_flg);
local_irq_enable();
local_fiq_enable();
return (u32)timespec_to_ns(&ts_idle)/1000;
}
