static ir_node *default_remat(ir_node *node, ir_node *after)
{
ir_node *const block = get_block(after);
ir_node *const copy = exact_copy(node);
set_nodes_block(copy, block);
sched_add_after(after, copy);
return copy;
}
static ir_node *arm_new_spill(ir_node *value, ir_node *after)
{
ir_node *block = get_block(after);
ir_graph *irg = get_irn_irg(after);
ir_node *frame = get_irg_frame(irg);
ir_node *mem = get_irg_no_mem(irg);
ir_mode *mode = get_irn_mode(value);
ir_node *store = new_bd_arm_Str(NULL, block, frame, value, mem, mode,
NULL, false, 0, true);
arch_add_irn_flags(store, arch_irn_flag_spill);
sched_add_after(after, store);
return store;
}
static ir_node *create_fpu_mode_spill(void *const env, ir_node *const state, bool const force, ir_node *const after)
{
(void)env;
if (!force && is_ia32_ChangeCW(state))
return NULL;
ir_node *spill;
ir_node *const block = get_nodes_block(state);
/* Don't spill the fpcw in unsafe mode. */
if (ia32_cg_config.use_unsafe_floatconv) {
spill = new_bd_ia32_FnstCWNOP(NULL, block, state);
} else {
ir_graph *const irg = get_irn_irg(state);
ir_node *const noreg = ia32_new_NoReg_gp(irg);
ir_node *const nomem = get_irg_no_mem(irg);
ir_node *const frame = get_irg_frame(irg);
spill = create_fnstcw(block, frame, noreg, nomem, state);
}
sched_add_after(skip_Proj(after), spill);
return spill;
}
