/*! \brief Main function of the example memory manager.
*
* This example shows how memory can be allocated from different
* memory spaces.
* The default allocation will get memory from the internal SRAM.
* By using the "memory space" functionality of the memory manager
* it is possible to use other memory spaces as resources like an
* attached SDRAM.
*/
int main(void)
{
void *some_space;
void *some_more_space;
void *some_space_in_sdram;
mspace sdram_msp;
// Switch to external oscillator 0.
pcl_switch_to_osc(PCL_OSC0, FOSC0, OSC0_STARTUP);
sdramc_init(FHSB_HZ);
// default allocation with C-library malloc from internal SRAM
some_space = malloc(512);
some_more_space = malloc(64);
// Create a new memory space the covers the SDRAM
sdram_msp = create_mspace_with_base((void*) SDRAM_START_ADDRESS, MEM_SPACE_SIZE, 0);
// allocate memory from the created memroy space
some_space_in_sdram = mspace_malloc(sdram_msp, 512);
while (true)
{
}
}
/**
* \brief Test SDRAMC initialize interface, through SDRAMC read/write access.
*
* \param test Current test case.
*/
static void run_sdramc_test(const struct test_case *test)
{
uint32_t ul;
uint32_t *pul = (uint32_t *)BOARD_SDRAM_ADDR;
/* Enable SMC peripheral clock */
pmc_enable_periph_clk(ID_SMC);
/* Complete SDRAM configuration */
sdramc_init((sdramc_memory_dev_t *)&SDRAM_MICRON_MT48LC16M16A2,
sysclk_get_cpu_hz());
for (ul = 0; ul < SDRAMC_ADDR_LINE_LENGTH; ++ul) {
pul[1 << ul] = SDRAMC_UNIT_TEST_CONST_WRITE_DATA;
}
for (ul = 0; ul < SDRAMC_ADDR_LINE_LENGTH; ++ul) {
test_assert_true(test,
pul[1 << ul] == SDRAMC_UNIT_TEST_CONST_WRITE_DATA,
"SDRAMC write test failed");
}
for (ul = 0; ul < SDRAMC_ADDR_LINE_LENGTH; ++ul) {
pul[1 << ul] = SDRAMC_UNIT_TEST_CONST_READ_DATA;
}
for (ul = 0; ul < SDRAMC_ADDR_LINE_LENGTH; ++ul) {
test_assert_true(test,
pul[1 << ul] == SDRAMC_UNIT_TEST_CONST_READ_DATA,
"SDRAMC read test failed");
}
}
/**
* \brief Run unit tests for MT48LC16m16a2tg7 SDRAM
* \return 0 which should never occur.
*/
int main (void)
{
const usart_serial_options_t usart_serial_options = {
.baudrate = CONF_TEST_BAUDRATE,
.charlength = CONF_TEST_CHARLENGTH,
.paritytype = CONF_TEST_PARITY,
.stopbits = CONF_TEST_STOPBITS,
};
sysclk_init();
board_init();
stdio_serial_init(CONF_TEST_USART, &usart_serial_options);
sdramc_init(sysclk_get_cpu_hz());
// Define all the test cases
DEFINE_TEST_CASE(data_integrity_test, NULL, run_data_integrity_test,
NULL, "Data integrity test");
// Put test case addresses in an array
DEFINE_TEST_ARRAY(ebi_sdram_tests) = {
&data_integrity_test,
};
// Define the test suite
DEFINE_TEST_SUITE(ebi_sdram_suite, ebi_sdram_tests,
"UC3 EBI driver w/ SDRAM test suite");
// Set up the test data pointer and run all tests in the suite
test_set_data(¶ms);
test_suite_run(&ebi_sdram_suite);
while (true);
return (0);
}
// Low level initing Soc
extern void low_level_init(void) {
// enable led 0
AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB27;
AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB27;
AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB27;
// enable led 1
AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB0;
AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB0;
AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB0;
// enable dbgu
dbgu_init(48000000, 115200);
// put first string
put_string("\n");
put_string("Start on 48MHz clock\n");
put_string("Switching to main clock\n");
// wait for stable
delay(120000);
// change clock to main clock
mck_init(AT91C_CKGR_MOSCEN | (0xff << 8));
mck_en();
// wait for stable
delay(120000);
// reinit dbgu on 16MHz msck
dbgu_init(16000000, 115200);
// put second string
put_string("\n");
put_string("Running on 16MHz clock\n");
// setup plla_value
put_string("Setup plla_value\nMultiplay: 210\nDivide: 16\nOutput clock: 210MHz\n");
put_string("Initing PLLA\n");
plla_init(plla_setup(16, 100, 2, 209));
put_string("PLLA inited, switching to PLLA clock\n");
delay(100000);
pllack_en(AT91C_PMC_MDIV_2);
dbgu_init(105000000, 115200);
delay(100000);
put_string("\n");
put_string("Running on 105MHz clock\n");
// init aic
aic_init(AT91C_AIC_BRANCH_OPCODE, aic_default,
aic_default, aic_spirious_int, 0);
// perform 8 end of interrupt command to make sure AIC will not lock out nIRQ
aic_acknowledge_irq();
aic_acknowledge_irq();
aic_acknowledge_irq();
aic_acknowledge_irq();
aic_acknowledge_irq();
aic_acknowledge_irq();
aic_acknowledge_irq();
aic_acknowledge_irq();
// setup basic exception vectors
aic_set_exception_vector((unsigned int *)0x0C, aic_fetch_abort);
aic_set_exception_vector((unsigned int *)0x10, aic_data_abort);
aic_set_exception_vector((unsigned int *)0x4, aic_undefined);
// initing ebi
ebi_init();
// initing sdramc
sdramc_init();
}
asmlinkage void __init sysinit(void)
{
sys_clk_khz = clock_pll(0, 0);
sys_clk_mhz = sys_clk_khz/1000;
wtm_init();
scm_init();
gpio_init();
fbcs_init();
sdramc_init();
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* At this stage the main oscillator is supposed to be enabled
* PCK = MCK = MOSC
*/
pmc_init_pll(0);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/* PCK = PLLA/2 = 3 * MCK */
pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
/* Switch MCK on PLLA output */
pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
/* Configure PLLB */
//pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/* Configure the EBI Slave Slot Cycle to 64 */
writel((readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40,
(AT91C_BASE_MATRIX + MATRIX_SCFG3));
/* Init timer */
timer_init();
/* Initialize dbgu */
initialize_dbgu();
#ifdef CONFIG_SDRAM
/* Initlialize sdram controller */
sdramc_init();
#endif
#ifdef CONFIG_USER_HW_INIT
hw_init_hook();
#endif
#if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY)
/* Init the recovery buttons pins */
recovery_buttons_hw_init();
#endif
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* At this stage the main oscillator is supposed to be enabled
* PCK = MCK = MOSC
*/
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/* PCK = PLLA = 2 * MCK */
pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
/* Switch MCK on PLLA output */
pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
/* Configure PLLB */
//pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
/* Enable External Reset */
writel(((0xA5 << 24) | AT91C_RSTC_URSTEN), AT91C_BASE_RSTC + RSTC_RMR);
/* Initialize matrix */
at91_matrix_hw_init();
/* Init timer */
timer_init();
/* Initialize dbgu */
initialize_dbgu();
#ifdef CONFIG_SDRAM
/* Initlialize sdram controller */
sdramc_init();
#endif
#ifdef CONFIG_USER_HW_INIT
hw_init_hook();
#endif
#if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY)
/* Init the recovery buttons pins */
recovery_buttons_hw_init();
#endif
}
void memories_initialization(void)
{
#ifdef CONF_BOARD_SMC_PSRAM
psram_init();
#endif
#ifdef CONF_BOARD_SRAM
sram_init();
#endif
#ifdef CONF_BOARD_SDRAMC
/* Enable SMC peripheral clock */
pmc_enable_periph_clk(ID_SMC);
/* Complete SDRAM configuration */
sdramc_init((sdramc_memory_dev_t *)&SDRAM_MICRON_MT48LC16M16A2,
sysclk_get_cpu_hz());
#endif
#ifdef CONF_BOARD_AT45DBX
at45dbx_init();
if (at45dbx_mem_check() != true) {
while (1) {
}
}
#endif
#ifdef CONF_BOARD_SD_MMC_HSMCI
uint8_t slot = 0;
sd_mmc_err_t err;
sd_mmc_init();
if (slot == sd_mmc_nb_slot()) {
slot = 0;
}
// Wait for a card and ready
do {
err = sd_mmc_check(slot);
if ((SD_MMC_ERR_NO_CARD != err)
&& (SD_MMC_INIT_ONGOING != err)
&& (SD_MMC_OK != err)) {
while (SD_MMC_ERR_NO_CARD != sd_mmc_check(slot)) {
}
}
} while (SD_MMC_OK != err);
#endif
}
void systemInit(void)
{
//Low-level initialization
_init_startup();
//Switch main clock to OSC0 (12MHz)
pm_switch_to_osc0(&AVR32_PM, OSC0_FREQ, AVR32_PM_OSCCTRL1_STARTUP_2048_RCOSC);
//Start OSC1 (11.2896MHz)
pm_enable_osc1_crystal(&AVR32_PM, OSC1_FREQ);
pm_enable_clk1(&AVR32_PM, AVR32_PM_OSCCTRL1_STARTUP_2048_RCOSC);
//Configure PLL0 (132MHz)
pm_pll_setup(&AVR32_PM, 0, 10, 1, 0, 16);
//Set PLL operating range (80 to 180MHz) and output divider (2)
pm_pll_set_option(&AVR32_PM, 0, 1, 1, 0);
//Start PLL0
pm_pll_enable(&AVR32_PM, 0);
//Wait for the PLL to lock
pm_wait_for_pll0_locked(&AVR32_PM);
//Set FLASH wait-state
flashc_set_wait_state(1);
//Switch main clock to PLL0
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
//Configure PLL1 (96MHz)
pm_pll_setup(&AVR32_PM, 1, 7, 1, 0, 16);
//Set PLL operating range (80 to 180MHz) and output divider (2)
pm_pll_set_option(&AVR32_PM, 1, 1, 1, 0);
//Start PLL1
pm_pll_enable(&AVR32_PM, 1);
//Wait for the PLL to lock
pm_wait_for_pll1_locked(&AVR32_PM);
//Set clock dividers for PBA, PBB and HSB clocks
pm_cksel(&AVR32_PM, 0, 0, 0, 0, 0, 0);
//Initialize SDRAM memory
sdramc_init(HSB_FREQ);
}
void __initialize_hardware(void)
{
/*******************************************************
* Out of reset, the low-level assembly code calls this
* routine to initialize the derivative modules for the
* board.
********************************************************/
//DM gpio_init();
fbcs_init();
sdramc_init();
/* enabling peripheral clocks */
MCF_PMM_PPMLR0 &= ~(MCF_PMM_PPMLR0_CD18); /* ICTRL0 */
MCF_PMM_PPMLR0 &= ~(MCF_PMM_PPMLR0_CD19); /* ICTRL1 */
MCF_PMM_PPMLR0 &= ~(MCF_PMM_PPMLR0_CD20); /* ICTRL2 */
initialize_exceptions();
}
/**
* \brief Application entry point for sdramc_example.
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
/* Initialize the system */
sysclk_init();
board_init();
sleepmgr_init();
/* Configure the console uart */
configure_console();
/* Output example information */
puts(STRING_HEADER);
/* Systick configuration */
if (SysTick_Config(SystemCoreClock / (1000))) {
puts("-F- Systick configuration error.\r");
}
/* Enable SMC peripheral clock */
pmc_enable_periph_clk(ID_SDRAMC);
/* Complete SDRAM configuration */
sdramc_init((sdramc_memory_dev_t *)&SDRAM_ISSI_IS42S16100E,
sysclk_get_cpu_hz());
sdram_enable_unaligned_support();
/* Test external SDRAM access */
puts("Test external SDRAM access. \r");
if (sdram_access_test() == SDRAMC_OK) {
puts("SDRAM access is successful.\n\r");
} else {
puts("SDRAM access is failed.\r");
}
if (sdram_benchmarks() == SDRAMC_OK) {
puts("SDRAM test: pass.\r");
}
for (;;) {
sleepmgr_enter_sleep();
}
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/* Adjust waitstates to access internal flash */
writel(AT91C_EEFC_FWS_6WS, AT91C_BASE_EEFC + EEFC_FMR);
/*
* At this stage the main oscillator is supposed to be enabled
* PCK = MCK = MOSC
*/
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);
/* PCK = PLLA = 2 * MCK */
pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
/* Switch MCK on PLLA output */
pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);
/* Configure PLLB */
//pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
#ifdef CONFIG_DEBUG
/* Initialize dbgu */
initialize_dbgu();
#endif
#ifdef CONFIG_SDRAM
/* Configure SDRAM Controller */
sdramc_init();
#endif
#ifdef CONFIG_USER_HW_INIT
hw_init_hook();
#endif
}
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* At this stage the main oscillator is supposed to be enabled
* PCK = MCK = MOSC
*/
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLL_SETTINGS);
/* PCK = PLL = 2 * MCK */
pmc_cfg_mck(MCKR_SETTINGS);
/* Switch MCK on PLLA output */
pmc_cfg_mck(MCKR_CSS_SETTINGS);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/* Init timer */
timer_init();
/* Initialize dbgu */
initialize_dbgu();
/* Initialize matrix configuration */
at91_matrix_hw_init();
#ifdef CONFIG_SDRAM
/* Configure SDRAM Controller */
sdramc_init();
#endif
#if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY)
/* Init the recovery buttons pins */
recovery_buttons_hw_init();
#endif
}
static void init_spi(void)
{
#if defined(WL_SPI)
int i;
#endif
#if defined(AT45DBX_SPI)
static const gpio_map_t AT45DBX_SPI_GPIO_MAP = {
{ AT45DBX_SPI_SCK_PIN, AT45DBX_SPI_SCK_FUNCTION },
{ AT45DBX_SPI_MISO_PIN, AT45DBX_SPI_MISO_FUNCTION },
{ AT45DBX_SPI_MOSI_PIN, AT45DBX_SPI_MOSI_FUNCTION },
{ AT45DBX_SPI_NPCS2_PIN, AT45DBX_SPI_NPCS2_FUNCTION },
};
#endif
#if defined(WL_SPI)
const gpio_map_t WL_SPI_GPIO_MAP = {
#if defined(WL_SPI_NPCS0)
WL_SPI_NPCS0,
#endif
WL_SPI_NPCS, WL_SPI_MISO, WL_SPI_MOSI, WL_SPI_SCK
};
#endif
#if defined(WL_SPI) || defined(AT45DBX_SPI)
spi_options_t spiOptions = {
.modfdis = 1 /* only param used by spi_initMaster() */
};
#endif
#if defined(AT45DBX_SPI)
gpio_enable_module(AT45DBX_SPI_GPIO_MAP,
sizeof(AT45DBX_SPI_GPIO_MAP) /
sizeof(AT45DBX_SPI_GPIO_MAP[0]));
spi_initMaster(AT45DBX_SPI, &spiOptions);
spi_selectionMode(AT45DBX_SPI, 0, 0, 0);
#endif
#if defined(WL_SPI)
/* same pins might be initialized twice here */
gpio_enable_module(WL_SPI_GPIO_MAP,
sizeof(WL_SPI_GPIO_MAP) /
sizeof(WL_SPI_GPIO_MAP[0]));
for (i = 0; i < sizeof(WL_SPI_GPIO_MAP)/sizeof(WL_SPI_GPIO_MAP[0]); i++)
gpio_enable_pin_pull_up(WL_SPI_GPIO_MAP[i].pin);
/* same SPI controller might be initialized again */
spi_initMaster(&WL_SPI, &spiOptions);
spi_selectionMode(&WL_SPI, 0, 0, 0);
#endif
#if defined(AT45DBX_SPI)
spi_enable(AT45DBX_SPI);
/* put up flash reset pin */
gpio_set_gpio_pin(AT45DBX_CHIP_RESET);
#endif
#if defined(WL_SPI)
spi_enable(&WL_SPI);
#endif
}
static void init_rs232(void)
{
#ifndef NO_SERIAL
#if defined(BOARD_RS232_0)
const gpio_map_t BOARD_RS232_0_GPIO_MAP = {
BOARD_RS232_0_TX,
BOARD_RS232_0_RX,
#if defined(BOARD_RS232_0_RTS) && defined (BOARD_RS232_0_CTS)
BOARD_RS232_0_RTS,
BOARD_RS232_0_CTS
#endif
};
#endif
#if defined(BOARD_RS232_1)
const gpio_map_t BOARD_RS232_1_GPIO_MAP = {
BOARD_RS232_1_TX,
BOARD_RS232_1_RX
#if defined(BOARD_RS232_1_RTS) && defined (BOARD_RS232_1_CTS)
BOARD_RS232_1_RTS,
BOARD_RS232_1_CTS
#endif
};
#endif
#if defined(BOARD_RS232_0)
gpio_enable_module(BOARD_RS232_0_GPIO_MAP,
sizeof(BOARD_RS232_0_GPIO_MAP) /
sizeof(BOARD_RS232_0_GPIO_MAP[0]));
#endif
#if defined(BOARD_RS232_1)
gpio_enable_module(BOARD_RS232_1_GPIO_MAP,
sizeof(BOARD_RS232_1_GPIO_MAP) /
sizeof(BOARD_RS232_1_GPIO_MAP[0]));
#endif
#endif /* NO_SERIAL */
}
static void init_printk(void)
{
#ifndef NO_SERIAL
#if defined(CONFIG_CONSOLE_PORT)
const usart_options_t usart_options = {
.baudrate = 57600,
.charlength = 8,
.paritytype = USART_NO_PARITY,
.stopbits = USART_1_STOPBIT,
.channelmode = USART_NORMAL_CHMODE
};
usart_init_rs232(&CONFIG_CONSOLE_PORT, &usart_options, FPBA_HZ);
#endif
#endif /* NO_SERIAL */
}
void board_init(void)
{
init_exceptions();
init_hmatrix();
init_sys_clocks();
init_interrupts();
init_rs232();
init_printk();
#ifdef WITH_SDRAM
sdramc_init(FHSB_HZ);
#endif
init_spi();
}
/*! \brief Sets the SDRAM Controller up, initializes the SDRAM found on the
* board and tests it.
*/
int main(void)
{
unsigned long sdram_size, progress_inc, i, j, tmp, noErrors = 0;
volatile unsigned long *sdram = SDRAM;
// Switch to external oscillator 0.
pcl_switch_to_osc(PCL_OSC0, FOSC0, OSC0_STARTUP);
// Initialize the debug USART module.
init_dbg_rs232(FOSC0);
// Calculate SDRAM size in words (32 bits).
sdram_size = SDRAM_SIZE >> 2;
print_dbg("\x0CSDRAM size: ");
print_dbg_ulong(SDRAM_SIZE >> 20);
print_dbg(" MB\r\n");
// Initialize the external SDRAM chip.
sdramc_init(FOSC0);
print_dbg("SDRAM initialized\r\n");
// Determine the increment of SDRAM word address requiring an update of the
// printed progression status.
progress_inc = (sdram_size + 50) / 100;
// Fill the SDRAM with the test pattern.
for (i = 0, j = 0; i < sdram_size; i++)
{
if (i == j * progress_inc)
{
LED_Toggle(LED_SDRAM_WRITE);
print_dbg("\rFilling SDRAM with test pattern: ");
print_dbg_ulong(j++);
print_dbg_char('%');
}
sdram[i] = i;
}
LED_Off(LED_SDRAM_WRITE);
print_dbg("\rSDRAM filled with test pattern \r\n");
// Recover the test pattern from the SDRAM and verify it.
for (i = 0, j = 0; i < sdram_size; i++)
{
if (i == j * progress_inc)
{
LED_Toggle(LED_SDRAM_READ);
print_dbg("\rRecovering test pattern from SDRAM: ");
print_dbg_ulong(j++);
print_dbg_char('%');
}
tmp = sdram[i];
if (tmp != i)
{
noErrors++;
}
}
LED_Off(LED_SDRAM_READ);
print_dbg("\rSDRAM tested: ");
print_dbg_ulong(noErrors);
print_dbg(" corrupted word(s) \r\n");
if (noErrors)
{
LED_Off(LED_SDRAM_ERRORS);
while (1)
{
LED_Toggle(LED_SDRAM_ERRORS);
cpu_delay_ms(200, FOSC0); // Fast blink means errors.
}
}
else
{
LED_Off(LED_SDRAM_OK);
while (1)
{
LED_Toggle(LED_SDRAM_OK);
cpu_delay_ms(1000, FOSC0); // Slow blink means OK.
}
}
}
int _init_startup(void)
{
/* Import the Exception Vector Base Address. */
extern void _evba;
#if configHEAP_INIT
extern void __heap_start__;
extern void __heap_end__;
portBASE_TYPE *pxMem;
#endif
/* Load the Exception Vector Base Address in the corresponding system register. */
Set_system_register( AVR32_EVBA, ( int ) &_evba );
board_init();
sysclk_init();
sdramc_init(sysclk_get_hsb_hz());
/* Enable exceptions. */
ENABLE_ALL_EXCEPTIONS();
/* Initialize interrupt handling. */
INTC_init_interrupts();
#if configHEAP_INIT
/* Initialize the heap used by malloc. */
for( pxMem = &__heap_start__; pxMem < ( portBASE_TYPE * )&__heap_end__; )
{
*pxMem++ = 0xA5A5A5A5;
}
#endif
/* Code section present if and only if the debug trace is activated. */
#if 0 //configDBG
{
static const gpio_map_t DBG_USART_GPIO_MAP =
{
{ configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
{ configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
};
static const usart_options_t DBG_USART_OPTIONS =
{
.baudrate = configDBG_USART_BAUDRATE,
.charlength = 8,
.paritytype = USART_NO_PARITY,
.stopbits = USART_1_STOPBIT,
.channelmode = USART_NORMAL_CHMODE
};
/* Initialize the USART used for the debug trace with the configured parameters. */
extern volatile avr32_usart_t *volatile stdio_usart_base;
stdio_usart_base = configDBG_USART;
gpio_enable_module( DBG_USART_GPIO_MAP,
sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configPBA_CLOCK_HZ);
}
#endif
// Don't-care value for GCC.
return 1;
}
/*-----------------------------------------------------------*/
/*
* malloc, realloc and free are meant to be called through respectively
* pvPortMalloc, pvPortRealloc and vPortFree.
* The latter functions call the former ones from within sections where tasks
* are suspended, so the latter functions are task-safe. __malloc_lock and
* __malloc_unlock use the same mechanism to also keep the former functions
* task-safe as they may be called directly from Newlib's functions.
* However, all these functions are interrupt-unsafe and SHALL THEREFORE NOT BE
* CALLED FROM WITHIN AN INTERRUPT, because __malloc_lock and __malloc_unlock do
* not call portENTER_CRITICAL and portEXIT_CRITICAL in order not to disable
* interrupts during memory allocation management as this may be a very time-
* consuming process.
*/
/*
* Lock routine called by Newlib on malloc / realloc / free entry to guarantee a
* safe section as memory allocation management uses global data.
* See the aforementioned details.
*/
void __malloc_lock(struct _reent *ptr);
void __malloc_lock(struct _reent *ptr)
{
vTaskSuspendAll();
}
/*
* Unlock routine called by Newlib on malloc / realloc / free exit to guarantee
* a safe section as memory allocation management uses global data.
* See the aforementioned details.
*/
void __malloc_unlock(struct _reent *ptr);
void __malloc_unlock(struct _reent *ptr)
{
xTaskResumeAll();
}
/*-----------------------------------------------------------*/
/* Added as there is no such function in FreeRTOS. */
void *pvPortRealloc( void *pv, size_t xWantedSize )
{
void *pvReturn;
vTaskSuspendAll();
{
pvReturn = realloc( pv, xWantedSize );
}
xTaskResumeAll();
return pvReturn;
}
