static void sdramc_init(void)
{
struct sdramc_register sdramc_config;
unsigned int reg;
sdramc_config.cr = AT91C_SDRAMC_NC_9
| AT91C_SDRAMC_NR_13
| AT91C_SDRAMC_CAS_2
| AT91C_SDRAMC_NB_4_BANKS
| AT91C_SDRAMC_DBW_32_BITS
| AT91C_SDRAMC_TWR_2
| AT91C_SDRAMC_TRC_7
| AT91C_SDRAMC_TRP_2
| AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8;
sdramc_config.tr = (MASTER_CLOCK * 7) / 1000000;
sdramc_config.mdr = AT91C_SDRAMC_MD_SDRAM;
sdramc_hw_init();
/* Initialize the matrix (memory voltage = 3.3) */
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS1A_SDRAMC;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
sdramc_initialize(&sdramc_config, AT91C_BASE_CS1);
}
static void sdramc0_init(void)
{
unsigned int reg;
struct sdramc_register sdramc_config;
#ifdef CONFIG_SDRAM_16BIT
sdramc_config.cr = AT91C_SDRAMC_NC_10 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2
| AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_16_BITS
| AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7
| AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2
| AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8;
#else
sdramc_config.cr = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2
| AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS
| AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7
| AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2
| AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8;
#endif /* #ifdef CONFIG_SDRAM_16BIT */
sdramc_config.tr = (MASTER_CLOCK * 7) / 1000000;
sdramc_config.mdr = AT91C_SDRAMC_MD_SDRAM;
sdramc_hw_init();
reg = readl(AT91C_BASE_CCFG + CCFG_EBI0CSA);
reg |= AT91C_VDDIOM_SEL_33V;
reg |= AT91C_EBI_CS1A_SDRAMC;
writel(reg, AT91C_BASE_CCFG + CCFG_EBI0CSA);
sdramc_initialize(&sdramc_config, AT91C_BASE_EBI0_CS1);
}
static void sdramc_init(void)
{
struct sdramc_register sdramc_config;
sdramc_config.cr = AT91C_SDRAMC_NC_9
| AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2
| AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS
| AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7
| AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2
| AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8;
sdramc_config.tr = (MASTER_CLOCK * 7) / 1000000;
sdramc_config.mdr = AT91C_SDRAMC_MD_SDRAM;
/* configure sdramc pins */
writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0));
writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0));
writel((1 << AT91C_ID_PIOC), (PMC_PCER + AT91C_BASE_PMC));
/* Initialize the matrix (memory voltage = 3.3) */
writel(readl(AT91C_BASE_CCFG + CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC,
AT91C_BASE_CCFG + CCFG_EBICSA);
sdramc_initialize(&sdramc_config, AT91C_BASE_CS1);
}
static void sdramc_init(void)
{
struct sdramc_register sdramc_config;
unsigned int reg;
#if defined(CONFIG_CPU_CLK_200MHZ)
sdramc_config.cr = AT91C_SDRAMC_NC_9
| AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2
| AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS
| AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7
| AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2
| AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8;
#endif
#if defined(CONFIG_CPU_CLK_266MHZ)
sdramc_config.cr = AT91C_SDRAMC_NC_9
| AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3
| AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS
| AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_9
| AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3
| AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10;
#endif
sdramc_config.tr = (MASTER_CLOCK * 7) / 1000000;
sdramc_config.mdr = AT91C_SDRAMC_MD_SDRAM;
/* configure sdramc pins */
writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_ASR(0));
writel(0xFFFF0000, AT91C_BASE_PIOC + PIO_PDR(0));
writel((1 << AT91C_ID_PIOC), (PMC_PCER + AT91C_BASE_PMC));
/* Initialize the matrix (memory voltage = 3.3) */
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS1A_SDRAMC;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
sdramc_initialize(&sdramc_config, AT91C_BASE_CS1);
}
static void sdramc_init(void)
{
struct sdramc_register sdramc_config;
sdramc_config.cr = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3
| AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS
| AT91C_SDRAMC_TWR_3 | AT91C_SDRAMC_TRC_9
| AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3
| AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10;
sdramc_config.tr = (MASTER_CLOCK * 7) / 1000000;
sdramc_config.mdr = AT91C_SDRAMC_MD_SDRAM;
sdramc_hw_init();
/* Initialize the matrix (memory voltage = 3.3) */
writel((readl(AT91C_BASE_CCFG + CCFG_EBICSA))
| AT91C_EBI_CS1A_SDRAMC | AT91C_VDDIOM_SEL_33V
| (0x01 << 17), /* set I/O slew selection */
AT91C_BASE_CCFG + CCFG_EBICSA);
sdramc_initialize(&sdramc_config, AT91C_BASE_CS1);
}
