/**
* @brief The basic entry point for board initialization.
*
* This is called as part of machine init (after arch init).
* This is again called with stack in SRAM, so not too many
* constructs possible here.
*
* @return void
*/
void board_init(void)
{
int in_sdram = running_in_sdram();
mux_config();
/* Dont reconfigure SDRAM while running in SDRAM! */
if (!in_sdram)
sdrc_init();
}
/**
* @brief The basic entry point for board initialization.
*
* This is called as part of machine init (after arch init).
* This is again called with stack in SRAM, so not too many
* constructs possible here.
*
* @return void
*/
static int sdp343x_board_init(void)
{
int in_sdram = omap3_running_in_sdram();
if (!in_sdram)
omap3_core_init();
mux_config();
if (!in_sdram)
sdrc_init();
return 0;
}
/**
* @brief The basic entry point for board initialization.
*
* This is called as part of machine init (after arch init).
* This is again called with stack in SRAM, so not too many
* constructs possible here.
*
* @return void
*/
static int omap3_evm_board_init(void)
{
int in_sdram = running_in_sdram();
omap3_core_init();
mux_config();
/* Dont reconfigure SDRAM while running in SDRAM! */
if (!in_sdram)
sdrc_init();
return 0;
}
int __init arch_board_early_init(void)
{
int rc;
/* Host virtual memory, device tree, heap is up.
* Do necessary early stuff like iomapping devices
* memory or boot time memory reservation here.
*/
/* The function omap3_beagle_init_early() of
* <linux>/arch/arm/mach-omap2/board-omap3beagle.c
* does the following:
* 1. Initialize Clock & Power Domains using function
* omap2_init_common_infrastructure() of
* <linux>/arch/arm/mach-omap2/io.c
* 2. Initialize & Reprogram Clock of SDRC using function
* omap2_sdrc_init() of <linux>/arch/arm/mach-omap2/sdrc.c
*/
/* Initialize Clock Mamagment */
if ((rc = cm_init())) {
return rc;
}
/* Initialize Power & Reset Mamagment */
if ((rc = prm_init())) {
return rc;
}
/* Enable I-clock for S32K timer
* Note: S32K is our reference clocksource and also used
* as clock reference for GPTs
*/
cm_setbits(OMAP3_WKUP_CM,
OMAP3_CM_ICLKEN_WKUP,
OMAP3_CM_ICLKEN_WKUP_EN_32KSYNC_M);
/* Initialize SDRAM Controller (SDRC) */
if ((rc = sdrc_init(OMAP3_SDRC_BASE,
OMAP3_SMS_BASE,
mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params))) {
return rc;
}
return 0;
}
/**********************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
* - Called path is with sram stack.
**********************************************************/
void s_init(void)
{
int in_sdram = running_in_sdram();
watchdog_init();
set_muxconf_regs();
delay(100);
try_unlock_sram();
if(!in_sdram)
prcm_init();
peripheral_enable();
icache_enable();
if (!in_sdram)
sdrc_init();
}
/******************************************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
* - Called path is with SRAM stack.
*****************************************************************************/
void s_init(void)
{
int in_sdram = is_running_in_sdram();
watchdog_init();
try_unlock_memory();
/*
* Right now flushing at low MPU speed.
* Need to move after clock init
*/
invalidate_dcache(get_device_type());
#ifndef CONFIG_ICACHE_OFF
icache_enable();
#endif
#ifdef CONFIG_L2_OFF
l2_cache_disable();
#else
l2_cache_enable();
#endif
/*
* Writing to AuxCR in U-boot using SMI for GP DEV
* Currently SMI in Kernel on ES2 devices seems to have an issue
* Once that is resolved, we can postpone this config to kernel
*/
if (get_device_type() == GP_DEVICE)
setup_auxcr();
set_muxconf_regs();
delay(100);
prcm_init();
per_clocks_enable();
/* FIXME: u-boot's sdrc setup is broken */
if (!in_sdram)
sdrc_init();
}
/**********************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
* - Called path is with sram stack.
**********************************************************/
void s_init(void)
{
int in_sdram = running_in_sdram();
/* u32 rev = get_cpu_rev(); unused as of now.. */
watchdog_init();
try_unlock_sram(); /* Do SRAM availability first - take care of permissions too */
set_muxconf_regs();
delay(100);
if (!in_sdram){
prcm_init();
}
peripheral_enable();
icache_enable();
if (!in_sdram)
sdrc_init();
}
