static void
ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct etrax_serial *s = opaque;
unsigned char ch = value;
D(CPUState *env = s->env);
D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value));
addr >>= 2;
switch (addr)
{
case RW_DOUT:
qemu_chr_fe_write(s->chr, &ch, 1);
s->regs[R_INTR] |= 3;
s->pending_tx = 1;
s->regs[addr] = value;
break;
case RW_ACK_INTR:
if (s->pending_tx) {
value &= ~1;
s->pending_tx = 0;
D(qemu_log("fixedup value=%x r_intr=%x\n",
value, s->regs[R_INTR]));
}
s->regs[addr] = value;
s->regs[R_INTR] &= ~value;
D(printf("r_intr=%x\n", s->regs[R_INTR]));
break;
default:
s->regs[addr] = value;
break;
}
ser_update_irq(s);
}
static void
ser_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
ETRAXSerial *s = opaque;
uint32_t value = val64;
unsigned char ch = val64;
D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value));
addr >>= 2;
switch (addr)
{
case RW_DOUT:
qemu_chr_fe_write(s->chr, &ch, 1);
s->regs[R_INTR] |= 3;
s->pending_tx = 1;
s->regs[addr] = value;
break;
case RW_ACK_INTR:
if (s->pending_tx) {
value &= ~1;
s->pending_tx = 0;
D(qemu_log("fixedup value=%x r_intr=%x\n",
value, s->regs[R_INTR]));
}
s->regs[addr] = value;
s->regs[R_INTR] &= ~value;
D(printf("r_intr=%x\n", s->regs[R_INTR]));
break;
default:
s->regs[addr] = value;
break;
}
ser_update_irq(s);
}
static void
ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct etrax_serial *s = opaque;
unsigned char ch = value;
D(CPUState *env = s->env);
D(printf ("%s %x %x\n", __func__, addr, value));
addr >>= 2;
switch (addr)
{
case RW_DOUT:
qemu_chr_write(s->chr, &ch, 1);
s->regs[R_INTR] |= 1;
s->pending_tx = 1;
s->regs[addr] = value;
break;
case RW_ACK_INTR:
s->regs[addr] = value;
if (s->pending_tx && (s->regs[addr] & 1)) {
s->regs[R_INTR] |= 1;
s->pending_tx = 0;
s->regs[addr] &= ~1;
}
break;
default:
s->regs[addr] = value;
break;
}
ser_update_irq(s);
}
static void serial_receive(void *opaque, const uint8_t *buf, int size)
{
struct etrax_serial_t *s = opaque;
s->r_intr |= 8;
s->rs_stat_din &= ~0xff;
s->rs_stat_din |= (buf[0] & 0xff);
s->rs_stat_din |= (1 << STAT_DAV); /* dav. */
ser_update_irq(s);
}
static void serial_receive(void *opaque, const uint8_t *buf, int size)
{
struct etrax_serial *s = opaque;
s->regs[R_INTR] |= 8;
s->regs[RS_STAT_DIN] &= ~0xff;
s->regs[RS_STAT_DIN] |= (buf[0] & 0xff);
s->regs[RS_STAT_DIN] |= (1 << STAT_DAV); /* dav. */
ser_update_irq(s);
}
static void serial_receive(void *opaque, const uint8_t *buf, int size)
{
struct etrax_serial *s = opaque;
int i;
/* Got a byte. */
if (s->rx_fifo_len >= 16) {
qemu_log("WARNING: UART dropped char.\n");
return;
}
for (i = 0; i < size; i++) {
s->rx_fifo[s->rx_fifo_pos] = buf[i];
s->rx_fifo_pos++;
s->rx_fifo_pos &= 15;
s->rx_fifo_len++;
}
ser_update_irq(s);
}
static void
ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct etrax_serial_t *s = opaque;
unsigned char ch = value;
D(CPUState *env = s->env);
switch (addr)
{
case RW_TR_CTRL:
D(printf("rw_tr_ctrl=%x\n", value));
s->rw_tr_ctrl = value;
break;
case RW_TR_DMA_EN:
D(printf("rw_tr_dma_en=%x\n", value));
s->rw_tr_dma_en = value;
break;
case RW_DOUT:
qemu_chr_write(s->chr, &ch, 1);
s->r_intr |= 1;
s->pending_tx = 1;
break;
case RW_ACK_INTR:
D(printf("rw_ack_intr=%x\n", value));
s->rw_ack_intr = value;
if (s->pending_tx && (s->rw_ack_intr & 1)) {
s->r_intr |= 1;
s->pending_tx = 0;
s->rw_ack_intr &= ~1;
}
break;
case RW_INTR_MASK:
D(printf("r_intr_mask=%x\n", value));
s->rw_intr_mask = value;
break;
default:
D(printf ("%s %x %x\n", __func__, addr, value));
break;
}
ser_update_irq(s);
}
