static int uart_post_init (struct NS16550 *com_port)
{
unsigned long reg;
unsigned long tmp;
unsigned long clk;
unsigned long udiv;
unsigned short bdiv;
int i;
for (i = 0; i < 3500; i++) {
if (in_8(&com_port->lsr) & UART_LSR_THRE)
break;
udelay (100);
}
#if defined(CONFIG_405EZ)
serial_divs(gd->baudrate, &udiv, &bdiv);
clk = tmp = reg = 0;
#else
#ifdef CONFIG_405EP
reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
clk = gd->cpu_clk;
tmp = CONFIG_SYS_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
if (udiv > UDIV_MAX) /* max. n bits for udiv */
udiv = UDIV_MAX;
reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
mtdcr (CPC0_UCR, reg);
#else /* CONFIG_405EP */
reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
udiv = 1;
reg |= CR0_EXTCLK_ENA;
#else
clk = gd->cpu_clk;
#ifdef CONFIG_SYS_405_UART_ERRATA_59
udiv = 31; /* Errata 59: stuck at 31 */
#else
tmp = CONFIG_SYS_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
if (udiv > UDIV_MAX) /* max. n bits for udiv */
udiv = UDIV_MAX;
#endif
#endif
reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
mtdcr (CPC0_CR0, reg);
#endif /* CONFIG_405EP */
tmp = gd->baudrate * udiv * 16;
bdiv = (clk + tmp / 2) / tmp;
#endif /* CONFIG_405EZ */
uart_post_init_common(com_port, bdiv);
return 0;
}
static int uart_post_init (struct NS16550 *com_port)
{
unsigned long reg = 0;
unsigned long udiv;
unsigned short bdiv;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
unsigned long tmp;
#endif
int i;
for (i = 0; i < 3500; i++) {
if (in_8(&com_port->lsr) & UART_LSR_THRE)
break;
udelay (100);
}
MFREG(UART0_SDR, reg);
reg &= ~CR0_MASK;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
reg |= CR0_EXTCLK_ENA;
udiv = 1;
tmp = gd->baudrate * 16;
bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
#else
/* For 440, the cpu clock is on divider chain A, UART on divider
* chain B ... so cpu clock is irrelevant. Get the "optimized"
* values that are subject to the 1/2 opb clock constraint
*/
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
/*
* Configure input clock to baudrate generator for all
* available serial ports here
*/
MTREG(UART0_SDR, reg);
#if defined(UART1_SDR)
MTREG(UART1_SDR, reg);
#endif
#if defined(UART2_SDR)
MTREG(UART2_SDR, reg);
#endif
#if defined(UART3_SDR)
MTREG(UART3_SDR, reg);
#endif
uart_post_init_common(com_port, bdiv);
return 0;
}
int serial_init_dev(unsigned long base)
{
unsigned long reg;
unsigned long udiv;
unsigned short bdiv;
#ifdef CFG_EXT_SERIAL_CLOCK
unsigned long tmp;
#endif
MFREG(UART0_SDR, reg);
reg &= ~CR0_MASK;
#ifdef CFG_EXT_SERIAL_CLOCK
reg |= CR0_EXTCLK_ENA;
udiv = 1;
tmp = gd->baudrate * 16;
bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
#else
/* For 440, the cpu clock is on divider chain A, UART on divider
* chain B ... so cpu clock is irrelevant. Get the "optimized"
* values that are subject to the 1/2 opb clock constraint
*/
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
/*
* Configure input clock to baudrate generator for all
* available serial ports here
*/
MTREG(UART0_SDR, reg);
#if defined(UART1_SDR)
MTREG(UART1_SDR, reg);
#endif
#if defined(UART2_SDR)
MTREG(UART2_SDR, reg);
#endif
#if defined(UART3_SDR)
MTREG(UART3_SDR, reg);
#endif
serial_init_common(base, udiv, bdiv);
return (0);
}
int serial_init_dev (unsigned long base)
{
unsigned long reg;
unsigned long tmp;
unsigned long clk;
unsigned long udiv;
unsigned short bdiv;
#ifdef CONFIG_405EX
clk = tmp = 0;
mfsdr(UART0_SDR, reg);
reg &= ~CR0_MASK;
#ifdef CFG_EXT_SERIAL_CLOCK
reg |= CR0_EXTCLK_ENA;
udiv = 1;
tmp = gd->baudrate * 16;
bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
#else
serial_divs(gd->baudrate, &udiv, &bdiv);
#endif
reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
/*
* Configure input clock to baudrate generator for all
* available serial ports here
*/
mtsdr(UART0_SDR, reg);
#if defined(UART1_SDR)
mtsdr(UART1_SDR, reg);
#endif
#elif defined(CONFIG_405EZ)
serial_divs(gd->baudrate, &udiv, &bdiv);
clk = tmp = reg = 0;
#else
#ifdef CONFIG_405EP
reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
clk = gd->cpu_clk;
tmp = CFG_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
if (udiv > UDIV_MAX) /* max. n bits for udiv */
udiv = UDIV_MAX;
reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
mtdcr (cpc0_ucr, reg);
#else /* CONFIG_405EP */
reg = mfdcr(cntrl0) & ~CR0_MASK;
#ifdef CFG_EXT_SERIAL_CLOCK
clk = CFG_EXT_SERIAL_CLOCK;
udiv = 1;
reg |= CR0_EXTCLK_ENA;
#else
clk = gd->cpu_clk;
#ifdef CFG_405_UART_ERRATA_59
udiv = 31; /* Errata 59: stuck at 31 */
#else
tmp = CFG_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
if (udiv > UDIV_MAX) /* max. n bits for udiv */
udiv = UDIV_MAX;
#endif
#endif
reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
mtdcr (cntrl0, reg);
#endif /* CONFIG_405EP */
tmp = gd->baudrate * udiv * 16;
bdiv = (clk + tmp / 2) / tmp;
#endif /* CONFIG_405EX */
serial_init_common(base, udiv, bdiv);
return (0);
}
static int uart_post_init (unsigned long dev_base)
{
unsigned long reg;
unsigned long tmp;
unsigned long clk;
unsigned long udiv;
unsigned short bdiv;
volatile char val;
int i;
for (i = 0; i < 3500; i++) {
if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
break;
udelay (100);
}
#if defined(CONFIG_405EZ)
serial_divs(gd->baudrate, &udiv, &bdiv);
clk = tmp = reg = 0;
#else
#ifdef CONFIG_405EP
reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
clk = gd->cpu_clk;
tmp = CONFIG_SYS_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
if (udiv > UDIV_MAX) /* max. n bits for udiv */
udiv = UDIV_MAX;
reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
mtdcr (cpc0_ucr, reg);
#else /* CONFIG_405EP */
reg = mfdcr(cntrl0) & ~CR0_MASK;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
udiv = 1;
reg |= CR0_EXTCLK_ENA;
#else
clk = gd->cpu_clk;
#ifdef CONFIG_SYS_405_UART_ERRATA_59
udiv = 31; /* Errata 59: stuck at 31 */
#else
tmp = CONFIG_SYS_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
if (udiv > UDIV_MAX) /* max. n bits for udiv */
udiv = UDIV_MAX;
#endif
#endif
reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
mtdcr (cntrl0, reg);
#endif /* CONFIG_405EP */
tmp = gd->baudrate * udiv * 16;
bdiv = (clk + tmp / 2) / tmp;
#endif /* CONFIG_405EZ */
out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
val = in8(dev_base + UART_LSR); /* clear line status */
val = in8(dev_base + UART_RBR); /* read receive buffer */
out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
return (0);
}
static int uart_post_init (unsigned long dev_base)
{
unsigned long reg = 0;
unsigned long udiv;
unsigned short bdiv;
volatile char val;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
unsigned long tmp;
#endif
int i;
for (i = 0; i < 3500; i++) {
if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
break;
udelay (100);
}
MFREG(UART0_SDR, reg);
reg &= ~CR0_MASK;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
reg |= CR0_EXTCLK_ENA;
udiv = 1;
tmp = gd->baudrate * 16;
bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
#else
/* For 440, the cpu clock is on divider chain A, UART on divider
* chain B ... so cpu clock is irrelevant. Get the "optimized"
* values that are subject to the 1/2 opb clock constraint
*/
serial_divs (gd->baudrate, &udiv, &bdiv);
#endif
reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
/*
* Configure input clock to baudrate generator for all
* available serial ports here
*/
MTREG(UART0_SDR, reg);
#if defined(UART1_SDR)
MTREG(UART1_SDR, reg);
#endif
#if defined(UART2_SDR)
MTREG(UART2_SDR, reg);
#endif
#if defined(UART3_SDR)
MTREG(UART3_SDR, reg);
#endif
out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
val = in8(dev_base + UART_LSR); /* clear line status */
val = in8(dev_base + UART_RBR); /* read receive buffer */
out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
return 0;
}
