int serial_init(const void * config_struct) {
const struct SerialConfig * config = (const struct SerialConfig *) config_struct;
serial_hw_init(config->baudrate, config->parity != DISABLED, config->parity == ODD);
return 0;
}
void cooling(void)
{
int i;
unsigned int tmp_data;
static struct meson_pm_config aml_pm_pdata = {
.pctl_reg_base = (void *)IO_APB_BUS_BASE,
.mmc_reg_base = (void *)APB_REG_ADDR(0x1000),
.hiu_reg_base = (void *)CBUS_REG_ADDR(0x1000),
.power_key = (1<<15),
.ddr_clk = 0x00120234, // 312m, 0x00110220, //384m
.sleepcount = 128,
//.set_vccx2 = set_vccx2, //Elvis Fool
.core_voltage_adjust = 5,
};
tvin_powerdown();
writel(0,P_WATCHDOG_TC);//disable Watchdog
//amp reset down GPIOX_51
clrbits_le32(P_PREG_FGPIO_O, 1<<19);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<19);
__udelay(1000);
//USB_PWR_CTL down x44
clrbits_le32(P_PREG_FGPIO_O, 1<<12);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<12);
//mute down x69
setbits_le32(P_PREG_GGPIO_O, 1<<5);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<5);
for(i=0; i<100; i++)
{
__udelay(1000);
}
//GPIOX_53 reset chip power ctrl BL_EN
setbits_le32(P_PREG_FGPIO_O, 1<<21);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<21);
//pwm x55
clrbits_le32(P_PREG_FGPIO_O, 1<<23);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<23);
//pwm b2
setbits_le32(P_PREG_GGPIO_O, 1<<10);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<10);
//pwm b3
setbits_le32(P_PREG_GGPIO_O, 1<<11);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<11);
for(i=0; i<100; i++)
{
__udelay(1000);
}
//GPIOX_48 LED_G
clrbits_le32(P_PREG_FGPIO_O, 1<<16);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<16);
//GPIOX_56 LED_R
setbits_le32(P_PREG_FGPIO_O, 1<<24);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<24);
//vcc_12v/24v power down GPIOX_70
//clrbits_le32(P_PREG_GGPIO_O, 1<<6);
//clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
serial_hw_init();
//setbits_le32(P_PERIPHS_PIN_MUX_2,((1<<29)|(1<<30)));
writel(0x18003033, P_UART1_CONTROL);
serial_puts("\nstandby...\n");
writel(0x209861f1, P_HHI_GCLK_MPEG0);
writel(0x208b8028, P_HHI_GCLK_MPEG1);
writel(0xfffffc07, P_HHI_GCLK_MPEG2);
writel(0xffc40021, P_HHI_GCLK_OTHER);
//analog off
WRITE_CBUS_REG(SAR_ADC_REG3, 0x3008510a);
//WRITE_CBUS_REG(VGHL_PWM_REG0, 0x0); //the same with off
//WRITE_CBUS_REG(WIFI_ADC_SAMPLING, 0x0); //the same with off
WRITE_APB_REG(ADC_EN_ADC, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_ADC_DAC, 0x0); //the same with off
//WRITE_AHB_REG(ADC_EN_CMLGEN_RES, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_SARADC, 0x0); //the same with off
//usb off
WRITE_CBUS_REG(PREI_USB_PHY_REG, 0x8040012b);
//clock off
//WRITE_CBUS_REG(HHI_DEMOD_CLK_CNTL, 0x400); //the same with off
//WRITE_CBUS_REG(HHI_SATA_CLK_CNTL, 0x0); //the same with off
//WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x207); //the same with off
//WRITE_CBUS_REG(HHI_WIFI_CLK_CNTL, 0x0); //the same with off
WRITE_CBUS_REG(HHI_VID_CLK_CNTL, 0x840e);
WRITE_CBUS_REG(HHI_AUD_CLK_CNTL, 0x800018);
WRITE_CBUS_REG(HHI_MALI_CLK_CNTL, 0x202);
WRITE_CBUS_REG(HHI_HDMI_CLK_CNTL, 0x203);
WRITE_CBUS_REG(HHI_MPEG_CLK_CNTL, 0x1083);
//pll off
WRITE_CBUS_REG(HHI_DEMOD_PLL_CNTL, 0x8232);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x8641);
WRITE_CBUS_REG(HHI_AUD_PLL_CNTL, 0xca80);
WRITE_CBUS_REG(HHI_OTHER_PLL_CNTL, 0x887d);
#ifdef SYSTEM_16K
if (READ_CBUS_REG(HHI_MPEG_CLK_CNTL)&(1<<8))
CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<9)); // xtal_rtc = rtc
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0x1, 0, 6); // devider = 2
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0, 12, 2); // clk81 src -> xtal_rtc
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal_rtc / devider
#else
CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0x1e, 0, 6); // devider = 30
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0, 12, 2); // clk81 src -> xtal_rtc
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal_rtc / devider
#endif
CLEAR_CBUS_REG_MASK(HHI_A9_CLK_CNTL, (1<<7)); // clka9 = xtal_rtc / 2
#ifdef SYSTEM_16K
SET_CBUS_REG_MASK(PREG_CTLREG0_ADDR, 1);
#endif
WRITE_CBUS_REG(HHI_A9_AUTO_CLK0,
(2 << 24) | // sleep select 1000uS timebase
(0x20 << 16) | // Set the delay wakeup time (32mS)
(0 << 5) | // don't clear the FIQ global mask
(0 << 4) | // don't clear the IRQ global mask
(2 << 2)); // Set interrupt wakeup only
WRITE_CBUS_REG(HHI_A9_AUTO_CLK1,
(0 << 20) | // start delay timebase
(1 << 12) | // 1uS enable delay
(1 << 8) | // 1uS gate delay
(1 << 0)); // 1us start delay
SET_CBUS_REG_MASK(HHI_A9_AUTO_CLK0, 1 << 0); //ENABLE: If this bit is set to 1, then the auto-clock ratio module will execute a change once the START pulses is generated.
SET_CBUS_REG_MASK(HHI_SYS_PLL_CNTL, (1<<15)); // turn off sys pll
/*
while(1)
{
if(serial_tstc()) break;
}*/
WRITE_CBUS_REG(0x2620, 0x10001);
WRITE_CBUS_REG(0x2621, 0x24);
WRITE_CBUS_REG(0x2622, 0);
WRITE_CBUS_REG(0x2623, 0);
WRITE_CBUS_REG(0x2624, 0);
enable_custom_trigger();
#ifdef CONFIG_MACH_MESON2_7366M_CST02
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_MASK, 1); //enable gpio interrupt
#endif
#ifdef CONFIG_MACH_MESON2_7366M_REFE03
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_MASK, 1); //enable gpio interrupt
#endif
tmp_data = READ_CBUS_REG(PREG_CTLREG0_ADDR);
WRITE_CBUS_REG(PREG_CTLREG0_ADDR, tmp_data | 0x1);
tmp_data = READ_CBUS_REG(IR_DEC_REG0);
WRITE_CBUS_REG(IR_DEC_REG0, tmp_data & 0xFFFFFF00);
tmp_data = READ_CBUS_REG(IR_DEC_REG1);
WRITE_CBUS_REG(IR_DEC_REG1, tmp_data | 0x00000001);
WRITE_CBUS_REG(IR_DEC_REG1, tmp_data & 0xFFFFFFFE);
//hub reset down x50
clrbits_le32(P_PREG_FGPIO_O, 1<<18);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<18);
//GPIOX_32 si2176_RESET down
clrbits_le32(P_PREG_FGPIO_O, 1<<0);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<0);
//PHY_RESET x57
clrbits_le32(P_PREG_FGPIO_O, 1<<25);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<25);
//close ddr
//gpiob_8
setbits_le32(P_PREG_GGPIO_O, 1<<16);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<16);
//gpiob_5
setbits_le32(P_PREG_GGPIO_O, 1<<13);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<13);
//gpiob_6
//setbits_le32(P_PREG_GGPIO_O, 1<<14);
//clrbits_le32(P_PREG_GGPIO_EN_N, 1<<14);
for(i=0; i<100; i++)
{
__udelay(1000);
}
meson_cpu_suspend(aml_pm_pdata);
for(i=0; i<100; i++)
{
__udelay(1000);
}
//GPIOX_54 reset chip panel power
clrbits_le32(P_PREG_FGPIO_O, 1<<22);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<22);
//pwm x55
setbits_le32(P_PREG_FGPIO_O, 1<<23);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<23);
//pwm b2
clrbits_le32(P_PREG_GGPIO_O, 1<<10);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<10);
//pwm b3
clrbits_le32(P_PREG_GGPIO_O, 1<<11);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<11);
for(i=0; i<300; i++)
{
__udelay(1000);
}
//vcc_12v/24v power on
setbits_le32(P_PREG_GGPIO_O, 1<<6);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
//setbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
for(i=0; i<800; i++)
{
__udelay(1000);
}
//GPIOX_53 reset chip power ctrl
//setbits_le32(P_PREG_FGPIO_O, 1<<21);
memory_pll_init(0,NULL);
serial_puts("\ngate clock on...\n");
writel(0xffffffff, P_HHI_GCLK_MPEG0);
writel(0xffffffff, P_HHI_GCLK_MPEG1);
writel(0xffffffff, P_HHI_GCLK_MPEG2);
writel(0xffffffff, P_HHI_GCLK_OTHER);
#if 0
//analog on
WRITE_CBUS_REG(SAR_ADC_REG3, 0x2008510a);
//WRITE_CBUS_REG(VGHL_PWM_REG0, 0x0); //the same with off
//WRITE_CBUS_REG(WIFI_ADC_SAMPLING, 0x0); //the same with off
//WRITE_APB_REG(ADC_EN_ADC, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_ADC_DAC, 0x0); //the same with off
//WRITE_AHB_REG(ADC_EN_CMLGEN_RES, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_SARADC, 0x0); //the same with off
//usb on
WRITE_CBUS_REG(PREI_USB_PHY_REG, 0x80400128);
//clock on
//WRITE_CBUS_REG(HHI_DEMOD_CLK_CNTL, 0x400); //the same with off
//WRITE_CBUS_REG(HHI_SATA_CLK_CNTL, 0x0); //the same with off
//WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x207); //the same with off
//WRITE_CBUS_REG(HHI_WIFI_CLK_CNTL, 0x0); //the same with off
WRITE_CBUS_REG(HHI_VID_CLK_CNTL, 0x840f);
WRITE_CBUS_REG(HHI_AUD_CLK_CNTL, 0x800018);
WRITE_CBUS_REG(HHI_MALI_CLK_CNTL, 0x302);
WRITE_CBUS_REG(HHI_HDMI_CLK_CNTL, 0x303);
WRITE_CBUS_REG(HHI_MPEG_CLK_CNTL, 0x1183);
//pll on
WRITE_CBUS_REG(HHI_DEMOD_PLL_CNTL, 0x232);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x641);
WRITE_CBUS_REG(HHI_AUD_PLL_CNTL, 0x4a80);
//WRITE_CBUS_REG(HHI_OTHER_PLL_CNTL, 0x87d);
#endif
return 0;
}
