void uart_hardware_init(void)
{
//HAS_CRITICAL_SECTION;
//ENTER_CRITICAL_SECTION();
//LEAVE_CRITICAL_SECTION();
if(uart_initialized == false) {
set_hbit(GPCTL,GPCTL_UART);
put_hvalue(GPPMB,0); // disable SIO bits 6 and 7
put_hvalue(GPPOB,0);
put_hvalue(GPPMA,0x0002); // RX is input (A0), TX is output (A1)
put_hvalue(GPPOA,0);
put_value(UARTIER,0); // no interrupts
put_value(UARTLCR,0x80); // enable access to divisor latch
put_value(UARTDLM,0);
put_value(UARTDLL,0x3E); // 57600 baud
put_value(UARTLCR,0x03);
put_value(UARTFCR,0xC7); // 14 byte trigger, cleared and buffered (auto set to normal FCR mode)
put_value(UARTMCR,0);
put_value(UARTIER,0x01); // RX
IRQ_HANDLER_TABLE[INT_UART]=uart_interrupt_handler;
set_wbit(ILC1,ILC1_ILR9 & ILC1_INT_LV3);
set_hbit(GPPMC, UART_EN); // set PIOC6(UART_EN) to output
set_hbit(GPPMC, UART_FORCEOFF); // set PIOC7(FORCEOFF) to output
set_hbit(GPCTL,GPCTL_UART);
put_hvalue(GPPMA,0x0002); // RX is input (A0), TX is output (A1)
put_hvalue(GPPOA,0);
clr_hbit(GPPOC,UART_EN);
set_hbit(GPPOC,UART_FORCEOFF); // this also drives FORCEON -- they are tied together
uart_initialized = true;
}
}
void init_i2c(void)
{
//Set secondary function for PB4 and PB5 => I2C bus : SCL + SDA
set_wbit(PORTSEL1,0x05000000);
//I2C peripheral select
set_hbit(I2CCTL,I2CCTL_I2CMEN);
//I2C slave address
put_hvalue(I2CSADR,0x0000);
//I2C bus speed
put_hvalue(I2CBC,0x0028); //100kHz @32MHz
//I2CBC = (APB_CLK)/( I2C bus speed x 8)
//I2C control register
put_hvalue(I2CCTL,0x0080);
//I2CCS=0
//enable I2C module
//selects standard mode 100kHz
}
uchar write_i2c(uchar addr_i2c, uchar *data, uchar nb_byte)
{
__disable_interrupt();
//Transmitted by master
set_hbit(I2CCTL,I2CCTL_I2CMTX);
//Continues clock upon completion
// clr_hbit(I2CCTL,I2CCTL_I2CCS);
//wait for I2C bus to be ready
if (!waiti2cmbb())
{
__enable_interrupt();
return FALSE;
}
/********************/
/* Send I2C address */
/********************/
//Write slave address
put_hvalue(I2CDR,(addr_i2c|I2C_WRITE_INSTR));
//Start condition
set_hbit(I2CCTL,I2CCTL_I2CMSTA);
//Look at arbitration
if((get_hvalue(I2CSR)&I2CSR_I2CMAL))
{
//Clear status
put_hvalue(I2CSR,0x0000);
__enable_interrupt();
return FALSE;
}
//wait for transfer to be completed
if (!waiti2cmcf())
{
__enable_interrupt();
return FALSE;
}
//Look at acknowledge
if((get_hvalue(I2CSR)&I2CSR_I2CRXAK))
{
//Stop condition
clr_hbit(I2CCTL,I2CCTL_I2CMSTA);
//Clear status
put_hvalue(I2CSR,0x0000);
__enable_interrupt();
return FALSE;
}
/*****************/
/* Send I2C data */
/*****************/
//Clear status
put_hvalue(I2CSR,0x0000);
while(nb_byte--)
{
//Write data
put_hvalue(I2CDR,*(data++));
//wait for transfer to be completed
if (!waiti2cmcf())
{
__enable_interrupt();
return FALSE;
}
//Look at acknowledge
if((get_hvalue(I2CSR)&I2CSR_I2CRXAK))
{
//Stop condition
clr_hbit(I2CCTL,I2CCTL_I2CMSTA);
//Clear status
put_hvalue(I2CSR,0x0000);
__enable_interrupt();
return FALSE;
}
//Clear completion bit
clr_hbit(I2CSR,I2CSR_I2CMCF);
}
/*************/
/* Stop I2C */
/*************/
//Clear status
put_hvalue(I2CSR,0x0000);
//Stop condition
clr_hbit(I2CCTL,I2CCTL_I2CMSTA);
__enable_interrupt();
return TRUE;
}
uchar read_i2c(uchar addr_i2c, uchar *data, uchar nb_byte)
{
__disable_interrupt();
//Transmitted by master
clr_hbit(I2CCTL,I2CCTL_I2CMTX);
//Continues clock upon completion
// clr_hbit(I2CCTL,I2CCTL_I2CCS);
//wait for I2C bus to be ready
if (!waiti2cmbb())
{
__enable_interrupt();
return FALSE;
}
/********************/
/* Send I2C address */
/********************/
//Write slave address
put_hvalue(I2CDR,(addr_i2c|I2C_READ_INSTR));
//Start condition
set_hbit(I2CCTL,I2CCTL_I2CMSTA);
//Look at arbitration
if((get_hvalue(I2CSR)&I2CSR_I2CMAL))
{
//Clear status
put_hvalue(I2CSR,0x0000);
__enable_interrupt();
return FALSE;
}
//wait for transfer to be completed
if (!waiti2cmcf())
{
__enable_interrupt();
return FALSE;
}
//Look at acknowledge
if((get_hvalue(I2CSR)&I2CSR_I2CRXAK))
{
//Stop condition
clr_hbit(I2CCTL,I2CCTL_I2CMSTA);
//Clear status
put_hvalue(I2CSR,0x0000);
__enable_interrupt();
return FALSE;
}
/********************/
/* Receive I2C data */
/********************/
do{
//Clear status
put_hvalue(I2CSR,0x0000);
//Check if last byte
if((nb_byte-1)==0)
break;
//wait for transfer to be completed
if (!waiti2cmcf())
{
__enable_interrupt();
return FALSE;
}
//Read data
*(data++)=get_value(I2CDR);
}while(nb_byte--);
//Send no ack
set_hbit(I2CCTL,I2CCTL_I2CTXAK);
//wait for transfer to be completed
if (!waiti2cmcf())
{
__enable_interrupt();
return FALSE;
}
//Read data
*(data++)=get_value(I2CDR);
//Clear status
put_hvalue(I2CSR,0x0000);
/*************/
/* Stop I2C */
/*************/
//Stop condition
clr_hbit(I2CCTL,I2CCTL_I2CMSTA);
clr_hbit(I2CCTL,I2CCTL_I2CTXAK);
__enable_interrupt();
return TRUE;
}
