/**
* inv_mpu_data_rdy_trigger_set_state() set datardy interrupt state
**/
static int inv_mpu_data_rdy_trigger_set_state(struct iio_trigger *trig,
bool state)
{
struct iio_dev *indio_dev = trig->private_data;
dev_dbg(&indio_dev->dev, "%s (%d)\n", __func__, state);
return set_inv_enable(indio_dev, state);
}
/**
* inv_init_config_mpu3050() - Initialize hardware, disable FIFO.
* @st: Device driver instance.
* Initial configuration:
* FSR: +/- 2000DPS
* DLPF: 42Hz
* FIFO rate: 50Hz
* Clock source: Gyro PLL
*/
int inv_init_config_mpu3050(struct iio_dev *indio_dev)
{
struct inv_reg_map_s *reg;
int result;
u8 data;
struct inv_mpu_iio_s *st = iio_priv(indio_dev);
if (st->chip_config.is_asleep)
return -EPERM;
/*reading AUX VDDIO register */
result = inv_i2c_read(st, REG_3050_AUX_VDDIO, 1, &data);
if (result)
return result;
data &= ~BIT_3050_VDDIO;
if (st->plat_data.level_shifter)
data |= BIT_3050_VDDIO;
result = inv_i2c_single_write(st, REG_3050_AUX_VDDIO, data);
if (result)
return result;
reg = &st->reg;
result = set_inv_enable(indio_dev, false);
if (result)
return result;
/*2000dps full scale range*/
result = inv_i2c_single_write(st, reg->lpf,
(INV_FSR_2000DPS << GYRO_CONFIG_FSR_SHIFT)
| INV_FILTER_42HZ);
if (result)
return result;
st->chip_config.fsr = INV_FSR_2000DPS;
st->chip_config.lpf = INV_FILTER_42HZ;
result = inv_i2c_single_write(st, reg->sample_rate_div,
ONE_K_HZ/INIT_FIFO_RATE - 1);
if (result)
return result;
st->chip_config.fifo_rate = INIT_FIFO_RATE;
st->irq_dur_ns = INIT_DUR_TIME;
st->chip_config.prog_start_addr = DMP_START_ADDR;
st->chip_config.gyro_enable = 1;
st->chip_config.gyro_fifo_enable = 1;
if ((SECONDARY_SLAVE_TYPE_ACCEL == st->plat_data.sec_slave_type) &&
st->mpu_slave) {
result = st->mpu_slave->setup(st);
if (result)
return result;
result = st->mpu_slave->set_fs(st, INV_FS_02G);
if (result)
return result;
result = st->mpu_slave->set_lpf(st, INIT_FIFO_RATE);
if (result)
return result;
st->chip_config.accl_enable = 1;
st->chip_config.accl_fifo_enable = 1;
}
return 0;
}
