static int davinci_spi_bufs_prep(struct spi_device *spi,
struct davinci_spi *davinci_spi)
{
int op_mode = 0;
/*
* REVISIT unless devices disagree about SPI_LOOP or
* SPI_READY (SPI_NO_CS only allows one device!), this
* should not need to be done before each message...
* optimize for both flags staying cleared.
*/
op_mode = SPIPC0_DIFUN_MASK
| SPIPC0_DOFUN_MASK
| SPIPC0_CLKFUN_MASK;
if (!(spi->mode & SPI_NO_CS))
op_mode |= 1 << spi->chip_select;
if (spi->mode & SPI_READY)
op_mode |= SPIPC0_SPIENA_MASK;
iowrite32(op_mode, davinci_spi->base + SPIPC0);
if (spi->mode & SPI_LOOP)
set_io_bits(davinci_spi->base + SPIGCR1,
SPIGCR1_LOOPBACK_MASK);
else
clear_io_bits(davinci_spi->base + SPIGCR1,
SPIGCR1_LOOPBACK_MASK);
return 0;
}
/*
* Interface to control the chip select signal
*/
static void davinci_spi_chipselect(struct spi_device *spi, int value)
{
struct davinci_spi *davinci_spi;
struct davinci_spi_platform_data *pdata;
u32 data1_reg_val = 0;
u32 tmp = 0;
davinci_spi = spi_master_get_devdata(spi->master);
pdata = davinci_spi->pdata;
if (spi->controller_data) {
if (spi->mode & SPI_CS_HIGH)
tmp = 1;
gpio_direction_output(spi->controller_data, !(value^tmp));
return;
}
/*
* Board specific chip select logic decides the polarity and cs
* line for the controller
*/
if (value == BITBANG_CS_INACTIVE) {
set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT);
data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
while ((ioread32(davinci_spi->base + SPIBUF)
& SPIBUF_RXEMPTY_MASK) == 0)
cpu_relax();
}
}
static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
{
struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
if (enable)
set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
else
clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
}
static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
{
struct davinci_spi *davinci_spi;
int int_status = 0;
int count, temp_count;
u8 conv = 1;
u8 tmp;
u32 data1_reg_val;
struct davinci_spi_dma *davinci_spi_dma;
int word_len, data_type, ret;
unsigned long tx_reg, rx_reg;
struct davinci_spi_platform_data *pdata;
struct device *sdev;
davinci_spi = spi_master_get_devdata(spi->master);
pdata = davinci_spi->pdata;
sdev = davinci_spi->bitbang.master->dev.parent;
davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
davinci_spi->tx = t->tx_buf;
davinci_spi->rx = t->rx_buf;
/* convert len to words based on bits_per_word */
conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
davinci_spi->count = t->len / conv;
INIT_COMPLETION(davinci_spi->done);
init_completion(&davinci_spi_dma->dma_rx_completion);
init_completion(&davinci_spi_dma->dma_tx_completion);
word_len = conv * 8;
if (word_len <= 8)
data_type = DAVINCI_DMA_DATA_TYPE_S8;
else if (word_len <= 16)
data_type = DAVINCI_DMA_DATA_TYPE_S16;
else if (word_len <= 32)
data_type = DAVINCI_DMA_DATA_TYPE_S32;
else
return -EINVAL;
ret = davinci_spi_bufs_prep(spi, davinci_spi);
if (ret)
return ret;
/* Put delay val if required */
iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
(pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
davinci_spi->base + SPIDELAY);
count = davinci_spi->count; /* the number of elements */
data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT;
/* CS default = 0xFF */
tmp = ~(0x1 << spi->chip_select);
clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT;
/* disable all interrupts for dma transfers */
clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
/* Disable SPI to write configuration bits in SPIDAT */
clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
/* Enable SPI */
set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
while ((ioread32(davinci_spi->base + SPIBUF)
& SPIBUF_RXEMPTY_MASK) == 0)
cpu_relax();
if (t->tx_buf) {
t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
DMA_TO_DEVICE);
if (dma_mapping_error(&spi->dev, t->tx_dma)) {
dev_dbg(sdev, "Unable to DMA map a %d bytes"
" TX buffer\n", count);
return -ENOMEM;
}
temp_count = count;
} else {
/* We need TX clocking for RX transaction */
t->tx_dma = dma_map_single(&spi->dev,
(void *)davinci_spi->tmp_buf, count + 1,
DMA_TO_DEVICE);
if (dma_mapping_error(&spi->dev, t->tx_dma)) {
dev_dbg(sdev, "Unable to DMA map a %d bytes"
" TX tmp buffer\n", count);
return -ENOMEM;
}
temp_count = count + 1;
}
edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
data_type, temp_count, 1, 0, ASYNC);
edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
if (t->rx_buf) {
/* initiate transaction */
iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count,
DMA_FROM_DEVICE);
if (dma_mapping_error(&spi->dev, t->rx_dma)) {
dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
count);
if (t->tx_buf != NULL)
dma_unmap_single(NULL, t->tx_dma,
count, DMA_TO_DEVICE);
return -ENOMEM;
}
edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
data_type, count, 1, 0, ASYNC);
edma_set_src(davinci_spi_dma->dma_rx_channel,
rx_reg, INCR, W8BIT);
edma_set_dest(davinci_spi_dma->dma_rx_channel,
t->rx_dma, INCR, W8BIT);
edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
data_type, 0);
}
if ((t->tx_buf) || (t->rx_buf))
edma_start(davinci_spi_dma->dma_tx_channel);
if (t->rx_buf)
edma_start(davinci_spi_dma->dma_rx_channel);
if ((t->rx_buf) || (t->tx_buf))
davinci_spi_set_dma_req(spi, 1);
if (t->tx_buf)
wait_for_completion_interruptible(
&davinci_spi_dma->dma_tx_completion);
if (t->rx_buf)
wait_for_completion_interruptible(
&davinci_spi_dma->dma_rx_completion);
dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE);
if (t->rx_buf)
dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE);
/*
* Check for bit error, desync error,parity error,timeout error and
* receive overflow errors
*/
int_status = ioread32(davinci_spi->base + SPIFLG);
ret = davinci_spi_check_error(davinci_spi, int_status);
if (ret != 0)
return ret;
/* SPI Framework maintains the count only in bytes so convert back */
davinci_spi->count *= conv;
return t->len;
}
/**
* davinci_spi_bufs - functions which will handle transfer data
* @spi: spi device on which data transfer to be done
* @t: spi transfer in which transfer info is filled
*
* This function will put data to be transferred into data register
* of SPI controller and then wait until the completion will be marked
* by the IRQ Handler.
*/
static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
{
struct davinci_spi *davinci_spi;
int int_status, count, ret;
u8 conv, tmp;
u32 tx_data, data1_reg_val;
u32 buf_val, flg_val;
struct davinci_spi_platform_data *pdata;
davinci_spi = spi_master_get_devdata(spi->master);
pdata = davinci_spi->pdata;
davinci_spi->tx = t->tx_buf;
davinci_spi->rx = t->rx_buf;
/* convert len to words based on bits_per_word */
conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
davinci_spi->count = t->len / conv;
INIT_COMPLETION(davinci_spi->done);
ret = davinci_spi_bufs_prep(spi, davinci_spi);
if (ret)
return ret;
/* Enable SPI */
set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
(pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
davinci_spi->base + SPIDELAY);
count = davinci_spi->count;
data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT;
tmp = ~(0x1 << spi->chip_select);
clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT;
while ((ioread32(davinci_spi->base + SPIBUF)
& SPIBUF_RXEMPTY_MASK) == 0)
cpu_relax();
/* Determine the command to execute READ or WRITE */
if (t->tx_buf) {
clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
while (1) {
tx_data = davinci_spi->get_tx(davinci_spi);
data1_reg_val &= ~(0xFFFF);
data1_reg_val |= (0xFFFF & tx_data);
buf_val = ioread32(davinci_spi->base + SPIBUF);
if ((buf_val & SPIBUF_TXFULL_MASK) == 0) {
iowrite32(data1_reg_val,
davinci_spi->base + SPIDAT1);
count--;
}
while (ioread32(davinci_spi->base + SPIBUF)
& SPIBUF_RXEMPTY_MASK)
cpu_relax();
/* getting the returned byte */
if (t->rx_buf) {
buf_val = ioread32(davinci_spi->base + SPIBUF);
davinci_spi->get_rx(buf_val, davinci_spi);
}
if (count <= 0)
break;
}
} else {
if (pdata->poll_mode) {
while (1) {
/* keeps the serial clock going */
if ((ioread32(davinci_spi->base + SPIBUF)
& SPIBUF_TXFULL_MASK) == 0)
iowrite32(data1_reg_val,
davinci_spi->base + SPIDAT1);
while (ioread32(davinci_spi->base + SPIBUF) &
SPIBUF_RXEMPTY_MASK)
cpu_relax();
flg_val = ioread32(davinci_spi->base + SPIFLG);
buf_val = ioread32(davinci_spi->base + SPIBUF);
davinci_spi->get_rx(buf_val, davinci_spi);
count--;
if (count <= 0)
break;
}
} else { /* Receive in Interrupt mode */
int i;
for (i = 0; i < davinci_spi->count; i++) {
set_io_bits(davinci_spi->base + SPIINT,
SPIINT_BITERR_INTR
| SPIINT_OVRRUN_INTR
| SPIINT_RX_INTR);
iowrite32(data1_reg_val,
davinci_spi->base + SPIDAT1);
while (ioread32(davinci_spi->base + SPIINT) &
SPIINT_RX_INTR)
cpu_relax();
}
iowrite32((data1_reg_val & 0x0ffcffff),
davinci_spi->base + SPIDAT1);
}
}
/*
* Check for bit error, desync error,parity error,timeout error and
* receive overflow errors
*/
int_status = ioread32(davinci_spi->base + SPIFLG);
ret = davinci_spi_check_error(davinci_spi, int_status);
if (ret != 0)
return ret;
/* SPI Framework maintains the count only in bytes so convert back */
davinci_spi->count *= conv;
return t->len;
}
static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
{
set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
}
/**
* davinci_spi_probe - probe function for SPI Master Controller
* @pdev: platform_device structure which contains plateform specific data
*/
static int davinci_spi_probe(struct platform_device *pdev)
{
struct spi_master *master;
struct davinci_spi *davinci_spi;
struct davinci_spi_platform_data *pdata;
struct resource *r, *mem;
resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
resource_size_t dma_eventq = SPI_NO_RESOURCE;
int i = 0, ret = 0;
pdata = pdev->dev.platform_data;
if (pdata == NULL) {
ret = -ENODEV;
goto err;
}
master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
if (master == NULL) {
ret = -ENOMEM;
goto err;
}
dev_set_drvdata(&pdev->dev, master);
davinci_spi = spi_master_get_devdata(master);
if (davinci_spi == NULL) {
ret = -ENOENT;
goto free_master;
}
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (r == NULL) {
ret = -ENOENT;
goto free_master;
}
davinci_spi->pbase = r->start;
davinci_spi->region_size = resource_size(r);
davinci_spi->pdata = pdata;
mem = request_mem_region(r->start, davinci_spi->region_size,
pdev->name);
if (mem == NULL) {
ret = -EBUSY;
goto free_master;
}
davinci_spi->base = (struct davinci_spi_reg __iomem *)
ioremap(r->start, davinci_spi->region_size);
if (davinci_spi->base == NULL) {
ret = -ENOMEM;
goto release_region;
}
davinci_spi->irq = platform_get_irq(pdev, 0);
if (davinci_spi->irq <= 0) {
ret = -EINVAL;
goto unmap_io;
}
ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED,
dev_name(&pdev->dev), davinci_spi);
if (ret)
goto unmap_io;
/* Allocate tmp_buf for tx_buf */
davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
if (davinci_spi->tmp_buf == NULL) {
ret = -ENOMEM;
goto irq_free;
}
davinci_spi->bitbang.master = spi_master_get(master);
if (davinci_spi->bitbang.master == NULL) {
ret = -ENODEV;
goto free_tmp_buf;
}
davinci_spi->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(davinci_spi->clk)) {
ret = -ENODEV;
goto put_master;
}
clk_enable(davinci_spi->clk);
master->bus_num = pdev->id;
master->num_chipselect = pdata->num_chipselect;
master->setup = davinci_spi_setup;
master->cleanup = davinci_spi_cleanup;
davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
davinci_spi->version = pdata->version;
use_dma = pdata->use_dma;
davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
if (davinci_spi->version == SPI_VERSION_2)
davinci_spi->bitbang.flags |= SPI_READY;
if (use_dma) {
r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
if (r)
dma_rx_chan = r->start;
r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
if (r)
dma_tx_chan = r->start;
r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
if (r)
dma_eventq = r->start;
}
if (!use_dma ||
dma_rx_chan == SPI_NO_RESOURCE ||
dma_tx_chan == SPI_NO_RESOURCE ||
dma_eventq == SPI_NO_RESOURCE) {
davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
use_dma = 0;
} else {
davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
davinci_spi->dma_channels = kzalloc(master->num_chipselect
* sizeof(struct davinci_spi_dma), GFP_KERNEL);
if (davinci_spi->dma_channels == NULL) {
ret = -ENOMEM;
goto free_clk;
}
for (i = 0; i < master->num_chipselect; i++) {
davinci_spi->dma_channels[i].dma_rx_channel = -1;
davinci_spi->dma_channels[i].dma_rx_sync_dev =
dma_rx_chan;
davinci_spi->dma_channels[i].dma_tx_channel = -1;
davinci_spi->dma_channels[i].dma_tx_sync_dev =
dma_tx_chan;
davinci_spi->dma_channels[i].eventq = dma_eventq;
}
dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
"Using RX channel = %d , TX channel = %d and "
"event queue = %d", dma_rx_chan, dma_tx_chan,
dma_eventq);
}
davinci_spi->get_rx = davinci_spi_rx_buf_u8;
davinci_spi->get_tx = davinci_spi_tx_buf_u8;
init_completion(&davinci_spi->done);
/* Reset In/OUT SPI module */
iowrite32(0, davinci_spi->base + SPIGCR0);
udelay(100);
iowrite32(1, davinci_spi->base + SPIGCR0);
/* Clock internal */
if (davinci_spi->pdata->clk_internal)
set_io_bits(davinci_spi->base + SPIGCR1,
SPIGCR1_CLKMOD_MASK);
else
clear_io_bits(davinci_spi->base + SPIGCR1,
SPIGCR1_CLKMOD_MASK);
/* master mode default */
set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
if (davinci_spi->pdata->intr_level)
iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
else
iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
ret = spi_bitbang_start(&davinci_spi->bitbang);
if (ret)
goto free_clk;
dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base);
if (!pdata->poll_mode)
dev_info(&pdev->dev, "Operating in interrupt mode"
" using IRQ %d\n", davinci_spi->irq);
return ret;
free_clk:
clk_disable(davinci_spi->clk);
clk_put(davinci_spi->clk);
put_master:
spi_master_put(master);
free_tmp_buf:
kfree(davinci_spi->tmp_buf);
irq_free:
free_irq(davinci_spi->irq, davinci_spi);
unmap_io:
iounmap(davinci_spi->base);
release_region:
release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
free_master:
kfree(master);
err:
return ret;
}
