int board_init(void) { u32 cpu_type = rmobile_get_cpu_type(); /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; if (cpu_type == RMOBILE_CPU_TYPE_R8A7795) { /* GSX: force power and clock supply */ writel(0x0000001F, SYSC_PWRONCR2); while (readl(SYSC_PWRSR2) != 0x000003E0) mdelay(20); mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); } /* USB1 pull-up */ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); /* Configure the HSUSB block */ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704); /* Choice USB0SEL */ clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, HSUSB_REG_UGCTRL2_USB0SEL_EHCI); /* low power status */ setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); return 0; }
/* PantherPoint PCH Power Management init */ static void ppt_pm_init(pci_dev_t dev) { debug("PantherPoint PM init\n"); pci_write_config8(dev, 0xa9, 0x47); setbits_le32(RCB_REG(0x2238), 1 << 0); setbits_le32(RCB_REG(0x228c), 1 << 0); setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14)); setbits_le16(RCB_REG(0x0900), 1 << 14); writel(0xc03b8400, RCB_REG(0x2304)); setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); clrsetbits_le32(RCB_REG(0x3314), 0x1f, 0xf); writel(0x054f0000, RCB_REG(0x3318)); writel(0x04000000, RCB_REG(0x3324)); setbits_le32(RCB_REG(0x3340), 0xfffff); setbits_le32(RCB_REG(0x3344), (1 << 1) | (1 << 0)); writel(0x0001c000, RCB_REG(0x3360)); writel(0x00061100, RCB_REG(0x3368)); writel(0x7f8fdfff, RCB_REG(0x3378)); writel(0x000003fd, RCB_REG(0x337c)); writel(0x00001000, RCB_REG(0x3388)); writel(0x0001c000, RCB_REG(0x3390)); writel(0x00000800, RCB_REG(0x33a0)); writel(0x00001000, RCB_REG(0x33b0)); writel(0x00093900, RCB_REG(0x33c0)); writel(0x24653002, RCB_REG(0x33cc)); writel(0x067388fe, RCB_REG(0x33d0)); clrsetbits_le32(RCB_REG(0x33d4), 0x0fff0fff, 0x00670060); writel(0x01010000, RCB_REG(0x3a28)); writel(0x01010404, RCB_REG(0x3a2c)); writel(0x01040000, RCB_REG(0x3a80)); clrsetbits_le32(RCB_REG(0x3a84), 0x0000ffff, 0x00001001); /* SATA 2/3 disabled */ setbits_le32(RCB_REG(0x3a84), 1 << 24); /* SATA 4/5 disabled */ setbits_le32(RCB_REG(0x3a88), 1 << 0); writel(0x00000001, RCB_REG(0x3a6c)); clrsetbits_le32(RCB_REG(0x2344), 0xff0000ff, 0xff00000c); clrsetbits_le32(RCB_REG(0x80c), 0xff << 20, 0x11 << 20); setbits_le32(RCB_REG(0x33a4), (1 << 0)); writel(0, RCB_REG(0x33c8)); setbits_le32(RCB_REG(0x21b0), 0xf); }
static int enable_pwm(void) { struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE; struct pwmss_ecap_regs *ecap; int ticks = PWM_TICKS; int duty = PWM_DUTY; ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE; /* enable clock */ setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN); /* TimeStam Counter register */ writel(0xdb9, &ecap->tsctr); /* config period */ writel(ticks - 1, &ecap->cap3); writel(ticks - 1, &ecap->cap1); setbits_le16(&ecap->ecctl2, (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0)); /* config duty */ writel(duty, &ecap->cap2); writel(duty, &ecap->cap4); /* start */ setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN); return 0; }
int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; /* USB1 pull-up */ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); /* Configure the HSUSB block */ mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704); /* Choice USB0SEL */ clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, HSUSB_REG_UGCTRL2_USB0SEL_EHCI); /* low power status */ setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); return 0; }