static void NovelReset(void)
{
SetWriteHandler(0x8000,0xFFFF,NovelWrite);
SetReadHandler(0x8000,0xFFFF,CartBR);
setprg32(0x8000,0);
setchr8(0);
}
void GenMMC3Power(void) {
if (UNIFchrrama) setchr8(0);
SetWriteHandler(0x8000, 0xBFFF, MMC3_CMDWrite);
SetWriteHandler(0xC000, 0xFFFF, MMC3_IRQWrite);
SetReadHandler(0x8000, 0xFFFF, CartBR);
A001B = A000B = 0;
setmirror(1);
if (mmc3opts & 1) {
if (WRAMSIZE == 1024) {
FCEU_CheatAddRAM(1, 0x7000, WRAM);
SetReadHandler(0x7000, 0x7FFF, MAWRAMMMC6);
SetWriteHandler(0x7000, 0x7FFF, MBWRAMMMC6);
} else {
FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
SetWriteHandler(0x6000, 0x6000 + ((WRAMSIZE - 1) & 0x1fff), CartBW);
SetReadHandler(0x6000, 0x6000 + ((WRAMSIZE - 1) & 0x1fff), CartBR);
setprg8r(0x10, 0x6000, 0);
}
if (!(mmc3opts & 2))
FCEU_dwmemset(WRAM, 0, WRAMSIZE);
}
MMC3RegReset();
if (CHRRAM)
FCEU_dwmemset(CHRRAM, 0, CHRRAMSIZE);
}
static void Sync(void)
{
setprg8(0x6000, reg);
setprg32r(1, 0x8000, 0);
setchr8(0);
setmirror(mirr);
}
static void Power(CartInfo *info)
{
setprg16(0x8000, 0xF);
setchr8(0);
latch = 0xFF;
Sync();
}
static void Sync(void)
{
setchr8(0);
setprg8r(0x10,0x6000,(reg&0xC0)>>6);
setprg32(0x8000,reg&0x1F);
// setmirror(((reg&0x20)>>5));
}
static void Sync(void)
{
setmirror(reg[0]);
setprg8r(0x10,0x6000,0);
setchr8(0);
setprg32(0x8000,(reg[1]+reg[2])&0xf);
}
static void MMC5CHRA(void)
{
int x;
switch(mmc5vsize&3)
{
case 0:setchr8(CHRBanksA[7]);
MMC5SPRVROM_BANK8(CHRBanksA[7]);
break;
case 1:setchr4(0x0000,CHRBanksA[3]);
setchr4(0x1000,CHRBanksA[7]);
MMC5SPRVROM_BANK4(0x0000,CHRBanksA[3]);
MMC5SPRVROM_BANK4(0x1000,CHRBanksA[7]);
break;
case 2:setchr2(0x0000,CHRBanksA[1]);
setchr2(0x0800,CHRBanksA[3]);
setchr2(0x1000,CHRBanksA[5]);
setchr2(0x1800,CHRBanksA[7]);
MMC5SPRVROM_BANK2(0x0000,CHRBanksA[1]);
MMC5SPRVROM_BANK2(0x0800,CHRBanksA[3]);
MMC5SPRVROM_BANK2(0x1000,CHRBanksA[5]);
MMC5SPRVROM_BANK2(0x1800,CHRBanksA[7]);
break;
case 3:
for(x=0;x<8;x++)
{
setchr1(x<<10,CHRBanksA[x]);
MMC5SPRVROM_BANK1(x<<10,CHRBanksA[x]);
}
break;
}
}
static DECLFW(Write2)
{
if(A==0x5101)
{
if(laststrobe&&!V)
{
trigger^=1;
}
laststrobe=V;
} else if(A==0x5100&&V==6) //damn thoose protected games
setprg32(0x8000,3);
else
switch (A&0x7300)
{
case 0x5200:
DRegs[0]=V;
Sync();
break;
case 0x5000:
DRegs[1]=V;
Sync();
if(!(DRegs[1]&0x80)&&(scanline<128)) setchr8(0);
break;
case 0x5300:
DRegs[2]=V;
break;
}
}
static void Sync(void) {
setprg16(0x8000, preg);
setprg16(0xC000, ~0);
setchr8(0);
if (mirr)
setmirror(mirr);
}
static void Sync(void)
{
setchr8(0);
setprg32(0x8000,~0);
setprg4(0xb800,reg0);
setprg4(0xc800,8+reg1);
}
static void Sync(void)
{
setchr8(0);
setprg8r(0x10,0x6000,0);
setprg32(0x8000,reg[1]>>1);
setmirror((reg[0]&1)^1);
}
static void Sync185(void) {
// little dirty eh? ;_)
if ((datareg & 3) && (datareg != 0x13)) // 1, 2, 3, 4, 5, 6
setchr8(0);
else
setchr8r(0x10, 0);
}
static void FDSInit(void)
{
memset(FDSRegs,0,sizeof(FDSRegs));
writeskip=DiskPtr=DiskSeekIRQ=0;
setmirror(1);
setprg8r(0,0xe000,0); // BIOS
setprg32r(1,0x6000,0); // 32KB RAM
setchr8(0); // 8KB CHR RAM
MapIRQHook=FDSFix;
GameStateRestore=FDSStateRestore;
SetReadHandler(0x4030,0x4030,FDSRead4030);
SetReadHandler(0x4031,0x4031,FDSRead4031);
SetReadHandler(0x4032,0x4032,FDSRead4032);
SetReadHandler(0x4033,0x4033,FDSRead4033);
SetWriteHandler(0x4020,0x4025,FDSWrite);
SetWriteHandler(0x6000,0xdfff,FDSRAMWrite);
SetReadHandler(0x6000,0xdfff,FDSRAMRead);
SetReadHandler(0xE000,0xFFFF,FDSBIOSRead);
IRQCount=IRQLatch=IRQa=0;
FDSSoundReset();
InDisk=0;
SelectDisk=0;
}
static void Sync185(void) {
/* little dirty eh? ;_) */
if ((datareg & 3) && (datareg != 0x13)) /* 1, 2, 3, 4, 5, 6 */
setchr8(0);
else
setchr8r(0x10, 0);
}
static void DREAMPower(void) {
latche = 0;
Sync();
setchr8(0);
SetReadHandler(0x8000, 0xFFFF, CartBR);
SetWriteHandler(0x5020, 0x5020, DREAMWrite);
}
static void NROM128Reset(CartInfo *info)
{
setprg16(0x8000,0);
setprg16(0xC000,0);
setchr8(0);
SetReadHandler(0x8000,0xFFFF,CartBR);
}
void GenMMC3Power(void) {
if (UNIFchrrama) setchr8(0);
SetWriteHandler(0x8000, 0xBFFF, MMC3_CMDWrite);
SetWriteHandler(0xC000, 0xFFFF, MMC3_IRQWrite);
SetReadHandler(0x8000, 0xFFFF, CartBR);
// KT-008 boards hack 2-in-1, TODO assign to new ines mapper, most dump of KT-boards on the net are mapper 4, so need database or goodnes fix support
SetWriteHandler(0x5000,0x5FFF, KT008HackWrite);
A001B = A000B = 0;
setmirror(1);
if (mmc3opts & 1) {
if (WRAMSIZE == 1024) {
FCEU_CheatAddRAM(1, 0x7000, WRAM);
SetReadHandler(0x7000, 0x7FFF, MAWRAMMMC6);
SetWriteHandler(0x7000, 0x7FFF, MBWRAMMMC6);
} else {
FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
SetWriteHandler(0x6000, 0x6000 + ((WRAMSIZE - 1) & 0x1fff), CartBW);
SetReadHandler(0x6000, 0x6000 + ((WRAMSIZE - 1) & 0x1fff), CartBR);
setprg8r(0x10, 0x6000, 0);
}
if (!(mmc3opts & 2))
FCEU_dwmemset(WRAM, 0, WRAMSIZE);
}
MMC3RegReset();
if (CHRRAM)
FCEU_dwmemset(CHRRAM, 0, CHRRAMSIZE);
}
static void BandaiSync(void)
{
if(is153)
{
int base=(reg[0]&1)<<4;
if(!UNIFchrrama) // SD Gundam Gaiden - Knight Gundam Monogatari 2 - Hikari no Kishi (J) uses WRAM but have CHRROM too
{
int i;
for(i=0; i<8; i++) setchr1(i<<10,reg[i]);
}
else
setchr8(0);
setprg16(0x8000,(reg[8]&0x0F)|base);
setprg16(0xC000,0x0F|base);
}
else
{
int i;
for(i=0; i<8; i++) setchr1(i<<10,reg[i]);
setprg16(0x8000,reg[8]);
setprg16(0xC000,~0);
}
switch(reg[9]&3)
{
case 0: setmirror(MI_V); break;
case 1: setmirror(MI_H); break;
case 2: setmirror(MI_0); break;
case 3: setmirror(MI_1); break;
}
}
static void Sync(void)
{
setchr8(0);
setprg8r(0x10,0x6000,0);
setprg32(0x8000,reg&0x1f);
setmirror(((reg&0x20)>>5)^1);
}
static void Sync181(void)
{
if(!(datareg&1)) // 7
setchr8(0);
else
setchr8r(0x10,0);
}
static void Sync(void)
{
setprg4r(1,0x5000,1);
setprg8r(1,0x6000,1);
setprg32(0x8000,prg);
setchr8(0);
}
static void UNLCC21Sync(void)
{
setprg32(0x8000,0);
setchr8(latche&1);
setmirror(MI_0+((latche&2)>>1));
}
static void Sync(void) {
setprg8(0x6000, reg[4]);
setprg8(0x8000, reg[1]);
setprg8(0xA000, reg[2]);
setprg8(0xC000, reg[3]);
setprg8(0xE000, ~0);
setchr8(0);
}
static void Sync(void) {
setprg8(0x6000, reg);
setprg8(0x8000, ~3);
setprg8(0xa000, ~2);
setprg8r(0x10, 0xc000, 0);
setprg8(0xe000, ~0);
setchr8(0);
}
static void Sync(void) {
if (mode) {
setprg16(0x8000, prg);
setprg16(0xC000, prg);
} else
setprg32(0x8000, prg >> 1);
setchr8(chr);
setmirror(mirr);
}
static void SyncLH10(void) {
setprg8(0x6000, ~1);
setprg8(0x8000, reg[6]);
setprg8(0xA000, reg[7]);
setprg8r(0x10, 0xC000, 0);
setprg8(0xE000, ~0);
setchr8(0);
setmirror(0);
}
static void Sync(void) {
setprg2r(0x10, 0x0800, 0);
setprg2r(0x10, 0x1000, 1);
setprg2r(0x10, 0x1800, 2);
setprg8r(0x10, 0x6000, 1);
setprg16(0x8000, 0);
setprg16(0xC000, ~0);
setchr8(0);
}
static void Sync(void) {
setprg32(0x8000, 0);
if(CHRsize[0] == 8192) {
setchr4(0x0000, latche & 1);
setchr4(0x1000, latche & 1);
} else {
setchr8(latche & 1); // actually, my bad, overdumped roms, the real CHR size if 8K
}
setmirror(MI_0 + (latche & 1));
}
static void Sync(void)
{
setprg4(0x5000,16);
setprg8(0x6000,2);
setprg8(0x8000,1);
setprg8(0xa000,0);
setprg8(0xc000,reg);
setprg8(0xe000,9);
setchr8(0);
}
static void Sync(void)
{
// setchr4(0x0000,(reg[0]&0x80) >> 7);
// setchr4(0x1000,(reg[0]&0x80) >> 7);
setchr8(0);
setprg8r(0x10,0x6000,0);
setprg16(0x8000,bs_tbl[reg[0]&0x7f]>>4);
setprg16(0xc000,bs_tbl[reg[0]&0x7f]&0xf);
setmirror(MI_V);
}
