static void mv_process_current_q(int first_block)
{
struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
struct sec_accel_config op;
switch (req_ctx->op) {
case COP_AES_ECB:
op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_ECB;
break;
case COP_AES_CBC:
default:
op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_CBC;
op.enc_iv = ENC_IV_POINT(SRAM_DATA_IV) |
ENC_IV_BUF_POINT(SRAM_DATA_IV_BUF);
if (first_block)
memcpy(cpg->sram + SRAM_DATA_IV, req->info, 16);
break;
}
if (req_ctx->decrypt) {
op.config |= CFG_DIR_DEC;
memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_dec_key,
AES_KEY_LEN);
} else {
op.config |= CFG_DIR_ENC;
memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_enc_key,
AES_KEY_LEN);
}
switch (ctx->key_len) {
case AES_KEYSIZE_128:
op.config |= CFG_AES_LEN_128;
break;
case AES_KEYSIZE_192:
op.config |= CFG_AES_LEN_192;
break;
case AES_KEYSIZE_256:
op.config |= CFG_AES_LEN_256;
break;
}
op.enc_p = ENC_P_SRC(SRAM_DATA_IN_START) |
ENC_P_DST(SRAM_DATA_OUT_START);
op.enc_key_p = SRAM_DATA_KEY_P;
setup_data_in();
op.enc_len = cpg->p.crypt_len;
memcpy(cpg->sram + SRAM_CONFIG, &op,
sizeof(struct sec_accel_config));
writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
/* GO */
writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
/*
* XXX: add timer if the interrupt does not occur for some mystery
* reason
*/
}
static void mv_process_hash_current(int first_block)
{
struct ahash_request *req = ahash_request_cast(cpg->cur_req);
struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
struct req_progress *p = &cpg->p;
struct sec_accel_config op = { 0 };
int is_last;
switch (req_ctx->op) {
case COP_SHA1:
default:
op.config = CFG_OP_MAC_ONLY | CFG_MACM_SHA1;
break;
case COP_HMAC_SHA1:
op.config = CFG_OP_MAC_ONLY | CFG_MACM_HMAC_SHA1;
break;
}
op.mac_src_p =
MAC_SRC_DATA_P(SRAM_DATA_IN_START) | MAC_SRC_TOTAL_LEN((u32)
req_ctx->
count);
setup_data_in();
op.mac_digest =
MAC_DIGEST_P(SRAM_DIGEST_BUF) | MAC_FRAG_LEN(p->crypt_len);
op.mac_iv =
MAC_INNER_IV_P(SRAM_HMAC_IV_IN) |
MAC_OUTER_IV_P(SRAM_HMAC_IV_OUT);
is_last = req_ctx->last_chunk
&& (p->hw_processed_bytes + p->crypt_len >= p->hw_nbytes)
&& (req_ctx->count <= MAX_HW_HASH_SIZE);
if (req_ctx->first_hash) {
if (is_last)
op.config |= CFG_NOT_FRAG;
else
op.config |= CFG_FIRST_FRAG;
req_ctx->first_hash = 0;
} else {
if (is_last)
op.config |= CFG_LAST_FRAG;
else
op.config |= CFG_MID_FRAG;
}
memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config));
writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
/* GO */
writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
/*
* XXX: add timer if the interrupt does not occur for some mystery
* reason
*/
}
static void cns3xxx_process_current_q(int first_block)
{
struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
struct cns3xxx_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
struct cns3xxx_req_ctx *req_ctx = ablkcipher_request_ctx(req);
struct sec_accel_config op;
struct accel_config in_op;
int i;
switch (req_ctx->op) {
case COP_AES_ECB:
op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_ECB;
break;
case COP_AES_CBC:
default:
op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_CBC;
//if (first_block)
{
memcpy(cpg->in_buf + IN_DATA_IV_P, req->info, 16);
}
break;
}
switch (ctx->key_len) {
case AES_KEYSIZE_128:
in_op.aes_type = AES_128;
//printk("AES 128\n");
break;
case AES_KEYSIZE_192:
in_op.aes_type = AES_192;
//printk("AES 192\n");
break;
case AES_KEYSIZE_256:
in_op.aes_type = AES_256;
//printk("AES 256\n");
break;
}
if (req_ctx->decrypt) {
in_op.enc = 0;
memcpy(cpg->in_buf + IN_DATA_KEY_P, ctx->aes_enc_key,
ctx->key_len);
} else {
in_op.enc = 1;
memcpy(cpg->in_buf + IN_DATA_KEY_P, ctx->aes_enc_key,
ctx->key_len);
}
setup_data_in(ctx->key_len);
in_op.msg_len = cpg->p.crypt_len;
in_op.inv.bufcnt = cpg->src_num_sgs;
for(i=0;i< cpg->src_num_sgs;i++)
{
in_op.inv.bufptr[i] = (u32 *)cpg->in_buf;
in_op.inv.bufsize[i] = in_op.msg_len;
}
in_op.outv.bufcnt = cpg->dst_num_sgs;
for(i=0;i< cpg->dst_num_sgs;i++)
{
in_op.outv.bufptr[i] = (u32 *)cpg->out_buf;
in_op.outv.bufsize[i] = in_op.msg_len;
}
/* GO */
// dump input data
#if 0
if (req_ctx->decrypt) {
printk("Key Pattern =");
for(i=0;i < 48;i++)
printk("%2x",cpg->in_buf[i]);
if(((i+1)%16)==0)
printk("\n");
}
#endif
if (p_KernAes != NULL)
{
(*p_KernAes)(n1_list->data, in_op.enc, in_op.aes_type, 0, in_op.msg_len, &in_op.inv, &in_op.outv,crypto_int, NULL); //(void *)csp1_request);
}
else
printk(KERN_CRIT "kernel_shim: Csp1EncryptAes: symbol_get(n1_EncryptAes) failed\n");
/*
* XXX: add timer if the interrupt does not occur for some mystery
* reason
*/
}
