int aw_pm_begin(suspend_state_t state)
{
PM_DBG("%d state begin:%d\n", state,debug_mask);
//set freq max
#ifdef CONFIG_CPU_FREQ_USR_EVNT_NOTIFY
//cpufreq_user_event_notify();
#endif
/*must init perfcounter, because delay_us and delay_ms is depandant perf counter*/
#ifndef GET_CYCLE_CNT
backup_perfcounter();
init_perfcounters (1, 0);
#endif
if(unlikely(debug_mask&PM_STANDBY_PRINT_REG)){
printk("before dev suspend , line:%d\n", __LINE__);
show_reg(SW_VA_CCM_IO_BASE, (CCU_REG_LENGTH)*4, "ccu");
show_reg(SW_VA_PORTC_IO_BASE, GPIO_REG_LENGTH*4, "gpio");
show_reg(SW_VA_TIMERC_IO_BASE, TMR_REG_LENGTH*4, "timer");
show_reg(SW_VA_TWI0_IO_BASE, TWI0_REG_LENGTH*4, "twi0");
show_reg(SW_VA_SRAM_IO_BASE, SRAM_REG_LENGTH*4, "sram");
if (userdef_reg_addr != 0 && userdef_reg_size != 0)
{
show_reg(userdef_reg_addr, userdef_reg_size*4, "user defined");
}
}
return 0;
}
int aw_pm_begin(suspend_state_t state)
{
struct cpufreq_policy *policy;
PM_DBG("%d state begin:%d\n", state,debug_mask);
//set freq max
#ifdef CONFIG_CPU_FREQ_USR_EVNT_NOTIFY
//cpufreq_user_event_notify();
#endif
backup_max_freq = 0;
backup_min_freq = 0;
policy = cpufreq_cpu_get(0);
if (!policy)
{
PM_DBG("line:%d cpufreq_cpu_get failed!\n", __LINE__);
goto out;
}
backup_max_freq = policy->max;
backup_min_freq = policy->min;
policy->user_policy.max= suspend_freq;
policy->user_policy.min = suspend_freq;
cpufreq_cpu_put(policy);
cpufreq_update_policy(0);
/*must init perfcounter, because delay_us and delay_ms is depandant perf counter*/
#ifndef GET_CYCLE_CNT
backup_perfcounter();
init_perfcounters (1, 0);
#endif
if(unlikely(debug_mask&PM_STANDBY_PRINT_REG)){
printk("before dev suspend , line:%d\n", __LINE__);
show_reg(SW_VA_CCM_IO_BASE, (CCU_REG_LENGTH)*4, "ccu");
show_reg(SW_VA_PORTC_IO_BASE, GPIO_REG_LENGTH*4, "gpio");
show_reg(SW_VA_TIMERC_IO_BASE, TMR_REG_LENGTH*4, "timer");
show_reg(SW_VA_TWI0_IO_BASE, TWI0_REG_LENGTH*4, "twi0");
show_reg(SW_VA_SRAM_IO_BASE, SRAM_REG_LENGTH*4, "sram");
if (userdef_reg_addr != 0 && userdef_reg_size != 0)
{
show_reg(userdef_reg_addr, userdef_reg_size*4, "user defined");
}
}
return 0;
out:
return -1;
}
/*
*********************************************************************************************************
* aw_pm_end
*
*Description: Notify the platform that system is in work mode now.
*
*Arguments : none
*
*Return : none
*
*Notes : This function is called by the PM core right after resuming devices, to indicate to
* the platform that the system has returned to the working state or
* the transition to the sleep state has been aborted. This function is opposited to
* aw_pm_begin function.
*********************************************************************************************************
*/
void aw_pm_end(void)
{
struct cpufreq_policy *policy;
#ifndef GET_CYCLE_CNT
#ifndef IO_MEASURE
restore_perfcounter();
#endif
#endif
pm_disable_watchdog(dogMode);
if (backup_max_freq != 0 && backup_min_freq != 0)
{
policy = cpufreq_cpu_get(0);
if (!policy)
{
printk("cpufreq_cpu_get err! check it! aw_pm_end:%d\n", __LINE__);
return;
}
policy->user_policy.max = backup_max_freq;
policy->user_policy.min = backup_min_freq;
cpufreq_cpu_put(policy);
cpufreq_update_policy(0);
}
if(unlikely(debug_mask&PM_STANDBY_PRINT_REG)){
printk("after dev suspend, line:%d\n", __LINE__);
show_reg(SW_VA_CCM_IO_BASE, (CCU_REG_LENGTH)*4, "ccu");
show_reg(SW_VA_PORTC_IO_BASE, GPIO_REG_LENGTH*4, "gpio");
show_reg(SW_VA_TIMERC_IO_BASE, TMR_REG_LENGTH*4, "timer");
show_reg(SW_VA_TWI0_IO_BASE, TWI0_REG_LENGTH*4, "twi0");
show_reg(SW_VA_SRAM_IO_BASE, SRAM_REG_LENGTH*4, "sram");
if (userdef_reg_addr != 0 && userdef_reg_size != 0)
{
show_reg(userdef_reg_addr, userdef_reg_size*4, "user defined");
}
}
PM_DBG("aw_pm_end!\n");
}
/*
*********************************************************************************************************
* aw_pm_end
*
*Description: Notify the platform that system is in work mode now.
*
*Arguments : none
*
*Return : none
*
*Notes : This function is called by the PM core right after resuming devices, to indicate to
* the platform that the system has returned to the working state or
* the transition to the sleep state has been aborted. This function is opposited to
* aw_pm_begin function.
*********************************************************************************************************
*/
void aw_pm_end(void)
{
#ifndef GET_CYCLE_CNT
#ifndef IO_MEASURE
restore_perfcounter();
#endif
#endif
pm_disable_watchdog(0);
if(unlikely(debug_mask&PM_STANDBY_PRINT_REG)){
printk("after dev suspend, line:%d\n", __LINE__);
show_reg(SW_VA_CCM_IO_BASE, (CCU_REG_LENGTH)*4, "ccu");
show_reg(SW_VA_PORTC_IO_BASE, GPIO_REG_LENGTH*4, "gpio");
show_reg(SW_VA_TIMERC_IO_BASE, TMR_REG_LENGTH*4, "timer");
show_reg(SW_VA_TWI0_IO_BASE, TWI0_REG_LENGTH*4, "twi0");
show_reg(SW_VA_SRAM_IO_BASE, SRAM_REG_LENGTH*4, "sram");
if (userdef_reg_addr != 0 && userdef_reg_size != 0)
{
show_reg(userdef_reg_addr, userdef_reg_size*4, "user defined");
}
}
PM_DBG("aw_pm_end!\n");
}
static void dump_afu_descriptor(struct cxl_afu *afu)
{
u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
int i;
#define show_reg(name, what) \
dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
val = AFUD_READ_INFO(afu);
show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
show_reg("num_of_processes", AFUD_NUM_PROCS(val));
show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
show_reg("req_prog_mode", val & 0xffffULL);
afu_cr_num = AFUD_NUM_CRS(val);
val = AFUD_READ(afu, 0x8);
show_reg("Reserved", val);
val = AFUD_READ(afu, 0x10);
show_reg("Reserved", val);
val = AFUD_READ(afu, 0x18);
show_reg("Reserved", val);
val = AFUD_READ_CR(afu);
show_reg("Reserved", (val >> (63-7)) & 0xff);
show_reg("AFU_CR_len", AFUD_CR_LEN(val));
afu_cr_len = AFUD_CR_LEN(val) * 256;
val = AFUD_READ_CR_OFF(afu);
afu_cr_off = val;
show_reg("AFU_CR_offset", val);
val = AFUD_READ_PPPSA(afu);
show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
val = AFUD_READ_PPPSA_OFF(afu);
show_reg("PerProcessPSA_offset", val);
val = AFUD_READ_EB(afu);
show_reg("Reserved", (val >> (63-7)) & 0xff);
show_reg("AFU_EB_len", AFUD_EB_LEN(val));
val = AFUD_READ_EB_OFF(afu);
show_reg("AFU_EB_offset", val);
for (i = 0; i < afu_cr_num; i++) {
val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
show_reg("CR Vendor", val & 0xffff);
show_reg("CR Device", (val >> 16) & 0xffff);
}
#undef show_reg
}
static void dump_cxl_config_space(struct pci_dev *dev)
{
int vsec;
u32 val;
dev_info(&dev->dev, "dump_cxl_config_space\n");
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
dev_info(&dev->dev, "BAR0: %#.8x\n", val);
pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
dev_info(&dev->dev, "BAR1: %#.8x\n", val);
pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
dev_info(&dev->dev, "BAR2: %#.8x\n", val);
pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
dev_info(&dev->dev, "BAR3: %#.8x\n", val);
pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
dev_info(&dev->dev, "BAR4: %#.8x\n", val);
pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
dev_info(&dev->dev, "BAR5: %#.8x\n", val);
dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
p1_base(dev), p1_size(dev));
dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
p2_base(dev), p2_size(dev));
dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
pci_resource_start(dev, 4), pci_resource_len(dev, 4));
if (!(vsec = find_cxl_vsec(dev)))
return;
#define show_reg(name, what) \
dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
pci_read_config_dword(dev, vsec + 0x0, &val);
show_reg("Cap ID", (val >> 0) & 0xffff);
show_reg("Cap Ver", (val >> 16) & 0xf);
show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
pci_read_config_dword(dev, vsec + 0x4, &val);
show_reg("VSEC ID", (val >> 0) & 0xffff);
show_reg("VSEC Rev", (val >> 16) & 0xf);
show_reg("VSEC Length", (val >> 20) & 0xfff);
pci_read_config_dword(dev, vsec + 0x8, &val);
show_reg("Num AFUs", (val >> 0) & 0xff);
show_reg("Status", (val >> 8) & 0xff);
show_reg("Mode Control", (val >> 16) & 0xff);
show_reg("Reserved", (val >> 24) & 0xff);
pci_read_config_dword(dev, vsec + 0xc, &val);
show_reg("PSL Rev", (val >> 0) & 0xffff);
show_reg("CAIA Ver", (val >> 16) & 0xffff);
pci_read_config_dword(dev, vsec + 0x10, &val);
show_reg("Base Image Rev", (val >> 0) & 0xffff);
show_reg("Reserved", (val >> 16) & 0x0fff);
show_reg("Image Control", (val >> 28) & 0x3);
show_reg("Reserved", (val >> 30) & 0x1);
show_reg("Image Loaded", (val >> 31) & 0x1);
pci_read_config_dword(dev, vsec + 0x14, &val);
show_reg("Reserved", val);
pci_read_config_dword(dev, vsec + 0x18, &val);
show_reg("Reserved", val);
pci_read_config_dword(dev, vsec + 0x1c, &val);
show_reg("Reserved", val);
pci_read_config_dword(dev, vsec + 0x20, &val);
show_reg("AFU Descriptor Offset", val);
pci_read_config_dword(dev, vsec + 0x24, &val);
show_reg("AFU Descriptor Size", val);
pci_read_config_dword(dev, vsec + 0x28, &val);
show_reg("Problem State Offset", val);
pci_read_config_dword(dev, vsec + 0x2c, &val);
show_reg("Problem State Size", val);
pci_read_config_dword(dev, vsec + 0x30, &val);
show_reg("Reserved", val);
pci_read_config_dword(dev, vsec + 0x34, &val);
show_reg("Reserved", val);
pci_read_config_dword(dev, vsec + 0x38, &val);
show_reg("Reserved", val);
pci_read_config_dword(dev, vsec + 0x3c, &val);
show_reg("Reserved", val);
pci_read_config_dword(dev, vsec + 0x40, &val);
show_reg("PSL Programming Port", val);
pci_read_config_dword(dev, vsec + 0x44, &val);
show_reg("PSL Programming Control", val);
pci_read_config_dword(dev, vsec + 0x48, &val);
show_reg("Reserved", val);
pci_read_config_dword(dev, vsec + 0x4c, &val);
show_reg("Reserved", val);
pci_read_config_dword(dev, vsec + 0x50, &val);
show_reg("Flash Address Register", val);
pci_read_config_dword(dev, vsec + 0x54, &val);
show_reg("Flash Size Register", val);
pci_read_config_dword(dev, vsec + 0x58, &val);
show_reg("Flash Status/Control Register", val);
pci_read_config_dword(dev, vsec + 0x58, &val);
show_reg("Flash Data Port", val);
#undef show_reg
}
/*
*********************************************************************************************************
* aw_pm_enter
*
*Description: Enter the system sleep state;
*
*Arguments : state system sleep state;
*
*Return : return 0 is process successed;
*
*Notes : this function is the core function for platform sleep.
*********************************************************************************************************
*/
static int aw_pm_enter(suspend_state_t state)
{
// asm volatile ("stmfd sp!, {r1-r12, lr}" );
normal_standby_func standby;
PM_DBG("enter state %d\n", state);
if(unlikely(debug_mask&PM_STANDBY_PRINT_REG)){
printk("after cpu suspend , line:%d\n", __LINE__);
show_reg(SW_VA_CCM_IO_BASE, (CCU_REG_LENGTH)*4, "ccu");
show_reg(SW_VA_PORTC_IO_BASE, GPIO_REG_LENGTH*4, "gpio");
show_reg(SW_VA_TIMERC_IO_BASE, TMR_REG_LENGTH*4, "timer");
show_reg(SW_VA_TWI0_IO_BASE, TWI0_REG_LENGTH*4, "twi0");
show_reg(SW_VA_SRAM_IO_BASE, SRAM_REG_LENGTH*4, "sram");
if (userdef_reg_addr != 0 && userdef_reg_size != 0)
{
show_reg(userdef_reg_addr, userdef_reg_size*4, "user defined");
}
}
standby_info.standby_para.axp_enable = standby_axp_enable;
if(NORMAL_STANDBY== standby_type){
standby = (int (*)(struct aw_pm_info *arg))SRAM_FUNC_START;
//move standby code to sram
memcpy((void *)SRAM_FUNC_START, (void *)&standby_bin_start, (int)&standby_bin_end - (int)&standby_bin_start);
/* config system wakeup evetn type */
if(PM_SUSPEND_MEM == state || PM_SUSPEND_STANDBY == state){
standby_info.standby_para.axp_src = AXP_MEM_WAKEUP;
}else if(PM_SUSPEND_BOOTFAST == state){
standby_info.standby_para.axp_src = AXP_BOOTFAST_WAKEUP;
}
standby_info.standby_para.event_enable = (SUSPEND_WAKEUP_SRC_EXINT | SUSPEND_WAKEUP_SRC_ALARM);
if (standby_timeout != 0)
{
standby_info.standby_para.event_enable |= (SUSPEND_WAKEUP_SRC_TIMEOFF);
standby_info.standby_para.time_off = standby_timeout;
}
/* goto sram and run */
printk("standby_mode:%d, standby_type:%d, line:%d\n",standby_mode, standby_type, __LINE__);
standby(&standby_info);
printk("standby_mode:%d, standby_type:%d, line:%d\n",standby_mode, standby_type, __LINE__);
}else if(SUPER_STANDBY == standby_type){
printk("standby_mode:%d, standby_type:%d, line:%d\n",standby_mode, standby_type, __LINE__);
print_call_info();
aw_super_standby(state);
}
pm_enable_watchdog();
print_call_info();
if(unlikely(debug_mask&PM_STANDBY_PRINT_REG)){
printk("after cpu suspend , line:%d\n", __LINE__);
show_reg(SW_VA_CCM_IO_BASE, (CCU_REG_LENGTH)*4, "ccu");
show_reg(SW_VA_PORTC_IO_BASE, GPIO_REG_LENGTH*4, "gpio");
show_reg(SW_VA_TIMERC_IO_BASE, TMR_REG_LENGTH*4, "timer");
show_reg(SW_VA_TWI0_IO_BASE, TWI0_REG_LENGTH*4, "twi0");
show_reg(SW_VA_SRAM_IO_BASE, SRAM_REG_LENGTH*4, "sram");
if (userdef_reg_addr != 0 && userdef_reg_size != 0)
{
show_reg(userdef_reg_addr, userdef_reg_size*4, "user defined");
}
}
// asm volatile ("ldmfd sp!, {r1-r12, lr}" );
return 0;
}
static void dump_afu_descriptor(struct cxl_afu *afu)
{
u64 val;
#define show_reg(name, what) \
dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
val = AFUD_READ_INFO(afu);
show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
show_reg("num_of_processes", AFUD_NUM_PROCS(val));
show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
show_reg("req_prog_mode", val & 0xffffULL);
val = AFUD_READ(afu, 0x8);
show_reg("Reserved", val);
val = AFUD_READ(afu, 0x10);
show_reg("Reserved", val);
val = AFUD_READ(afu, 0x18);
show_reg("Reserved", val);
val = AFUD_READ_CR(afu);
show_reg("Reserved", (val >> (63-7)) & 0xff);
show_reg("AFU_CR_len", AFUD_CR_LEN(val));
val = AFUD_READ_CR_OFF(afu);
show_reg("AFU_CR_offset", val);
val = AFUD_READ_PPPSA(afu);
show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
val = AFUD_READ_PPPSA_OFF(afu);
show_reg("PerProcessPSA_offset", val);
val = AFUD_READ_EB(afu);
show_reg("Reserved", (val >> (63-7)) & 0xff);
show_reg("AFU_EB_len", AFUD_EB_LEN(val));
val = AFUD_READ_EB_OFF(afu);
show_reg("AFU_EB_offset", val);
#undef show_reg
}
