/*
* タイマの起動処理
*/
void
target_timer_initialize(intptr_t exinf)
{
CLOCK cyc;
uint32_t tmp;
#ifdef SYSTIC_USE_CALIBRATION
/* CALIBRATIONレジスタの値を使用 */
cyc = (sil_rew_mem((void *)SYSTIC_CALIBRATION) & SYSTIC_TENMS) / 10;
#else
cyc = TO_CLOCK(TIC_NUME, TIC_DENO) - 1;
#endif /* SYSTIC_USE_CALIBRATION */
/* 停止 */
tmp = sil_rew_mem((void *)SYSTIC_CONTROL_STATUS);
tmp &= ~SYSTIC_ENABLE;
sil_wrw_mem((void *)SYSTIC_CONTROL_STATUS, tmp);
sil_wrw_mem((void *)SYSTIC_RELOAD_VALUE, cyc);
sil_wrw_mem((void *)SYSTIC_CURRENT_VALUE, cyc);
tmp = sil_rew_mem((void *)SYSTIC_CONTROL_STATUS);
#ifdef SYSTIC_USE_STCLK
/* 外部クロックの使用 */
tmp |= SYSTIC_ENABLE;
#else
/* プロセッサクロックの使用 */
tmp |= SYSTIC_ENABLE|SYSTIC_CLKSOURCE;
#endif /* SYSTIC_USE_STCLK */
sil_wrw_mem((void *)SYSTIC_CONTROL_STATUS, tmp);
}
void
at91skyeye_init_uart(void)
{
/* 受信データの格納先アドレスの設定 */
sil_wrw_mem((void *)(USART0_RPR), (uint32_t)(&usart_rev_buf));
sil_wrw_mem((void *)(USART0_RCR), 0x0001);
}
/*
* ターゲット依存の初期化
*/
void
target_initialize(void)
{
uint32_t reg;
/*
* チップ依存の初期化
*/
chip_initialize();
/*
* Emulation Baseboardの割込みモードの設定
*/
sil_wrw_mem(EB_SYS_LOCK, EB_SYS_LOCK_UNLOCK); /* ロック解除 */
reg = sil_rew_mem(EB_SYS_PLD_CTRL1);
reg &= ~EB_SYS_PLD_CTRL1_INTMODE_MASK;
reg |= EB_SYS_PLD_CTRL1_INTMODE_NEW_NODCC;
sil_wrw_mem(EB_SYS_PLD_CTRL1, reg);
sil_wrw_mem(EB_SYS_LOCK, EB_SYS_LOCK_LOCK); /* ロック */
/*
* UARTを初期化
*/
#ifndef TOPPERS_OMIT_TECS
tPutLogCT11MPCore_initialize();
#endif /* TOPPERS_OMIT_TECS */
}
/*
* CPUインタフェースの初期化
*/
void
gicc_initialize(void)
{
/*
* CPUインタフェースをディスエーブル
*/
sil_wrw_mem(GICC_CTLR, GICC_CTLR_DISABLE);
/*
* 割込み優先度マスクを最低優先度に設定
*/
gicc_set_priority((GIC_PRI_LEVEL - 1) << GIC_PRI_SHIFT);
/*
* 割込み優先度の全ビット有効に
*/
sil_wrw_mem(GICC_BPR, 0U);
/*
* アクティブな割込みがあれば，EOIによりクリアする
*/
sil_wrw_mem(GICC_EOIR, sil_rew_mem(GICC_IAR));
/*
* CPUインタフェースをイネーブル
*/
#ifdef TOPPERS_SAFEG_SECURE
sil_wrw_mem(GICC_CTLR, (GICC_CTLR_FIQEN|GICC_CTLR_ENABLEGRP1
|GICC_CTLR_ENABLEGRP0));
#else /* TOPPERS_SAFEG_SECURE */
sil_wrw_mem(GICC_CTLR, GICC_CTLR_ENABLE);
#endif /* TOPPERS_SAFEG_SECURE */
}
SIOPCB *
uart_opn_por(ID siopid, VP_INT exinf){
SIOPCB *siopcb;
const SIOPINIB *siopinib;
siopcb = get_siopcb(siopid);
siopinib = siopcb->siopinib;
#ifndef USE_JTAG_UART
// sil_wrw_mem(UART_DIVISOR, UART_DIVISOR_VAL);
sil_wrw_mem((VP)UART_STATUS, 0x00);
/*
* 受信割り込み許可
*/
sil_wrw_mem((VP)UART_CONTROL, UART_STATUS_RRDY);
#else
sil_wrw_mem((VP)JTAG_UART_CONTROL,JTAG_UART_CONTROL_RIE);
#endif /* USE_JTAG_UART */
siopcb->exinf = exinf;
siopcb->getready = siopcb->putready = FALSE;
siopcb->openflag = TRUE;
return(siopcb);
}
Inline void set_port_pull(uint32_t reg, uint_t p, bool_t up)
{
if (up) {
sil_wrw_mem((void*)GPIO_BSRR(reg), 0x01 << p);
} else {
sil_wrw_mem((void*)GPIO_BRR(reg), 0x01 << p);
}
}
void Buzzer(uint8_t buzzer)
{
if (buzzer == BUZZER_ON){
sil_wrw_mem((void *)FIO2SET0,sil_rew_mem((void *)FIO2SET0) | (0x1<<1) ); /*p2.0 high*/
}else {
sil_wrw_mem((void *)FIO2CLR0,sil_rew_mem((void *)FIO2CLR0) | (0x1<<1) ); /*p2.0 low*/
}
}
void LED_Output(uint8_t ledvalue)
{
sil_wrw_mem((void *)FIO3SET2,(0xf0 & (ledvalue<<4)));
sil_wrw_mem((void *)FIO3SET3,(0x0f & (ledvalue>>4)));
sil_wrw_mem((void *)FIO3CLR2,(0xf0 & ((~ledvalue)<<4)));
sil_wrw_mem((void *)FIO3CLR3,(0x0f & ((~ledvalue)>>4)));
}
void
at91skyeye_init_uart(uint_t siopid)
{
SIOPCB *p_siopcb = get_siopcb(siopid);
/* 受信データの格納先アドレスの設定 */
sil_wrw_mem((void *)(USART0_RPR), (uint32_t)(&(p_siopcb->usart_rev_buf)));
sil_wrw_mem((void *)(USART0_RCR), 0x0001);
}
ERCD RTC_Start(void)
{
/*clear the interrupt bits must do this to let the alarm pin to be low*/
sil_wrw_mem((void *)RTC_ILR, 0x7);
/*enable rtc clock*/
sil_wrw_mem((void *)RTC_CCR, 0x11);
return ERCD_OK;
}
void Buzzer_Init(void)
{
sil_wrw_mem((void *)SCS,sil_rew_mem((void *)SCS)|0x00000001); /*set GPIOx to use Fast I/O */
sil_wrw_mem((void *)PINSEL10,0); /*ETM interface is disabled. must set this*/
sil_wrw_mem((void *)PINSEL4,sil_rew_mem((void *)PINSEL4) & (~(0x3<<2)) ); /*set GPIOx to use Fast I/O */
sil_wrw_mem((void *)PINMODE4,sil_rew_mem((void *)PINMODE4) & (~(0x3<<2)) ); /*p2.0 pull up*/
sil_wrw_mem((void *)FIO2DIR0,sil_rew_mem((void *)FIO2DIR0) | (0x1<<1) ); /*p2.0 output*/
}
/*
* 送信する文字の書き込み
*/
Inline void
uart_putchar(SIOPCB *siopcb, UB c)
{
#ifndef USE_JTAG_UART
sil_wrw_mem((VP)UART_TXDATA, c);
#else
sil_wrw_mem((VP)JTAG_UART_DATA,c);
#endif /* USE_JTAG_UART */
}
void
pl310_init(uint32_t aux_val, uint32_t aux_mask)
{
uint32_t tmp;
uint32_t aux;
uint32_t cache_id;
uint32_t prefetch;
uint32_t prefetch_val = 0;
uint32_t power;
int ways;
/* L2キャッシュがすでにオンになっているか確認する */
tmp = sil_rew_mem((void*)(RMA1_L2CACHE_BASE + PL310_CTRL));
/* L2キャッシュが無効の場合のみ初期化を実施する */
if ( !(tmp & 1) ) {
cache_id = sil_rew_mem((void*)(RMA1_L2CACHE_BASE + PL310_CACHE_ID));
aux = sil_rew_mem((void*)(RMA1_L2CACHE_BASE + PL310_AUX_CTRL));
prefetch = sil_rew_mem((void*)(RMA1_L2CACHE_BASE + PL310_PREFETCH_CTRL));
power = sil_rew_mem((void*)(RMA1_L2CACHE_BASE + PL310_POWER_CTRL));
if (aux & (1 << 16)) {
ways = 16;
}
else {
ways = 8;
}
aux_val |= 1 << 22;
aux_val |= 1 << 29;
prefetch_val |= 1 << 29;
aux_val |= 1 << 28;
prefetch_val |= 1 << 28;
if ((cache_id & 0x3f) > 0x6) {
prefetch_val |= 1 << 30;
}
pl310_way_mask = (1 << ways) - 1;
aux &= aux_mask;
aux |= aux_val;
prefetch |= prefetch_val;
sil_wrw_mem((void*)(RMA1_L2CACHE_BASE + PL310_AUX_CTRL), aux);
sil_wrw_mem((void*)(RMA1_L2CACHE_BASE + PL310_PREFETCH_CTRL), prefetch);
sil_wrw_mem((void*)(RMA1_L2CACHE_BASE + PL310_POWER_CTRL), power);
pl310_inv_all();
sil_wrw_mem((void*)(RMA1_L2CACHE_BASE + PL310_CTRL), 1);
}
}
/*
* 受信した文字の取り出し
*/
Inline uint8_t
uart_getchar(SIOPCB *p_siopcb)
{
char c;
c = usart_rev_buf;
sil_wrw_mem((void *)(p_siopcb->p_siopinib->us_rpr), (uint32_t)(&usart_rev_buf));
sil_wrw_mem((void *)(p_siopcb->p_siopinib->us_rcr), 0x0001);
return(c);
}
void
uart_cls_por(SIOPCB *siopcb){
#ifndef USE_JTAG_UART
/* 割込み禁止 */
sil_wrw_mem((VP)UART_CONTROL, 0x00);
#else
sil_wrw_mem((VP)JTAG_UART_CONTROL,0x00);
#endif /* USE_JTAG_UART */
siopcb->openflag = FALSE;
siopcb->sendflag = FALSE;
}
/*
* 受信割込み禁止
*/
Inline void
uart_disable_rcv(SIOPCB *siopcb)
{
#ifndef USE_JTAG_UART
sil_wrw_mem((VP)UART_CONTROL,
sil_rew_mem((VP)UART_CONTROL)&~UART_STATUS_RRDY);
#else
sil_wrw_mem((VP)JTAG_UART_CONTROL,
sil_rew_mem((VP)JTAG_UART_CONTROL)&~JTAG_UART_CONTROL_RIE);
#endif /* USE_JTAG_UART */
}
void UART_PrintChar (uint8_t ch)
{
#if UART_PORT == 1
while (!(sil_rew_mem((void *)U1LSR) & 0x20)); /* wait until U1THR is empty.*/
sil_wrw_mem((void *)U1THR, ch);
#elif UART_PORT == 0
while (!(sil_rew_mem((void *)U0LSR) & 0x20)); /* wait until U1THR is empty.*/
sil_wrw_mem((void *)U0THR, ch);
#endif
}
/*
* 送信割込み禁止
*/
Inline void
uart_disable_send(SIOPCB *siopcb)
{
#ifndef USE_JTAG_UART
sil_wrw_mem((VP)UART_CONTROL,
sil_rew_mem((VP)UART_CONTROL)&~UART_CONTROL_ITRD);
#else
sil_wrw_mem((VP)JTAG_UART_CONTROL,
sil_rew_mem((VP)JTAG_UART_CONTROL)&~JTAG_UART_CONTROL_WIE);
#endif /* USE_JTAG_UART */
}
void timer2_capinit(void)
{
sil_wrw_mem(PCONP,sil_rew_mem(PCONP)|(1<<22));/*power on timer2*/
sil_wrw_mem(PCLKSEL1,(PCLKSEL1&(~(0x3<<12)))|(0x1<<12));/*pclk of timer is cclk*/
sil_wrw_mem(PINSEL0,sil_rew_mem(PINSEL0)|(0x3<<8)); /*p0.4 as cap2*/
sil_wrw_mem(T2PR,0); /*prescale counter is 0*/
sil_wrw_mem(T2IR,0xff); /*reset the interrupts*/
sil_wrw_mem(T2TCR,0x02); /*disable and reset counter*/
sil_wrw_mem(T2CTCR,0x00); /*timer mode,capture on rising edge CAP2.0 for TIMER2*/
sil_wrw_mem(T2MCR,0x00); /*disable match control*/
sil_wrw_mem(T2CCR,0x05); /*capture rising and falling edge cr0 load TC and generate interrupt*/
sil_wrw_mem(T2TCR,0x01); /*start counter*/
}
void LED_Init(void)
{
sil_wrw_mem((void *)SCS,sil_rew_mem((void *)SCS)|0x00000001); /*set GPIOx to use Fast I/O */
/* P3[20] - p3[27] =>LEDS as GPIOs*/
sil_wrw_mem((void *)PINSEL7,sil_rew_mem((void *)PINSEL7)&0xff0000ff);
/*select P320 - P327 pull_up*/
sil_wrw_mem((void *)PINMODE7,sil_rew_mem((void *)PINSEL7)&0xff0000ff);
/* P320-P327 as output */
sil_wrw_mem((void *)FIO3DIR2,sil_rew_mem((void *)FIO3DIR2)|0x000000f0);
sil_wrw_mem((void *)FIO3DIR3,sil_rew_mem((void *)FIO3DIR3)|0x0000000f);
}
ERCD RTC_Init(void)
{
/*power on the rtc*/
sil_wrw_mem((void *)PCONP,sil_rew_mem((void *)PCONP)|(1<<9));
/*don't compare seconds*/
sil_wrw_mem((void *)RTC_AMR, 0x01);
sil_wrw_mem((void *)RTC_CIIR, 0x0);
sil_wrw_mem((void *)RTC_CISS, 0x0);
/*RTC clock source select as RTC*/
sil_wrw_mem((void *)RTC_CCR, 0x10);
return ERCD_OK;
}
static void
set_iomuxc(uint32_t mux_ctl_offset, uint32_t mux_mode_val,
uint32_t sel_input_offset, uint32_t sel_input_val,
uint32_t pad_ctl_offset, uint32_t pad_ctl_val)
{
if (mux_ctl_offset)
sil_wrw_mem((uint32_t*)(IOMUXC_BASE + mux_ctl_offset), mux_mode_val);
if (sel_input_offset)
sil_wrw_mem((uint32_t*)(IOMUXC_BASE + sel_input_offset), sel_input_val);
if (pad_ctl_offset)
sil_wrw_mem((uint32_t*)(IOMUXC_BASE + pad_ctl_offset), pad_ctl_val);
}
void set_init_moudlestop_setting(){
/* power management setting*/
/* unlock register access */
sil_wrh_mem((void *)(SYSTEM_PRCR_ADDR), SYSTEM_PRKEY | SYSTEM_PRC1);
//enable RSPI0
sil_wrw_mem((void*)SYSTEM_MSTPCRA_ADDR, 0x46FFFFFF); //reset MSTPCRA
sil_wrw_mem((void*)SYSTEM_MSTPCRB_ADDR, 0xFFFFFFFF); //reset MSTPCRB
sil_wrw_mem((void*)SYSTEM_MSTPCRC_ADDR, 0xFFFF0000); //reset MSTPCRC
//lock register access
sil_wrh_mem((void *)(SYSTEM_PRCR_ADDR), SYSTEM_PRKEY );
/* end power management setting */
}
static inline void pl310_inv_all(void)
{
/* invalidate all ways */
sil_wrw_mem((void*)(RMA1_L2CACHE_BASE + PL310_INV_WAY), pl310_way_mask);
cache_wait_way((uint32_t *)(RMA1_L2CACHE_BASE+PL310_INV_WAY), pl310_way_mask);
cache_sync();
}
ERCD RTC_Stop(void)
{
/*disable rtc clock*/
sil_wrw_mem((void *)RTC_CCR,sil_rew_mem((void *)PCONP)&(~(1<<0)));
return ERCD_OK;
}
/*
* 受信割込み禁止
*/
Inline void
uart_disable_rcv(SIOPCB *siopcb)
{
unsigned long tmp = sil_rew_mem((VP)(siopcb->siopinib->uart_base+TOFF_UART_IER));
tmp &= ~US_ERXI;
sil_wrw_mem((VP)(siopcb->siopinib->uart_base+TOFF_UART_IER), tmp);
}
/*
* CPU Interface の終了
*/
void
gicc_stop(void)
{
#ifndef GICC_NO_INIT
sil_wrw_mem((void *)(GICC_CTLR), 0);
#endif /* GICC_NO_INIT */
}
/*
* 送信割込み許可
*/
Inline void
uart_enable_send(SIOPCB *siopcb)
{
unsigned long tmp = sil_rew_mem((VP)(siopcb->siopinib->uart_base+TOFF_UART_IER));
tmp |= US_ETXI;
sil_wrw_mem((VP)(siopcb->siopinib->uart_base+TOFF_UART_IER), tmp);
}
/*
* SIOポートのクローズ
*/
void
xuartps_cls_por(SIOPCB *p_siopcb)
{
if (p_siopcb->opened) {
/*
* 送受信のディスエーブル
*/
sil_wrw_mem(XUARTPS_CR(p_siopcb->p_siopinib->base),
XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS | XUARTPS_CR_STOPBRK);
/*
* 全割込みをディスエーブル
*/
sil_wrw_mem(XUARTPS_IDR(p_siopcb->p_siopinib->base), XUARTPS_IXR_ALL);
p_siopcb->opened = false;
}
}
ERCD RTC_SetTime(RTCTime Time)
{
/*ctc reset*/
sil_wrw_mem((void *)RTC_CCR,sil_rew_mem((void *)RTC_CCR)|(1<<1));
/*RTC current time set*/
sil_wrw_mem((void *)RTC_SEC, Time.RTC_Sec);
sil_wrw_mem((void *)RTC_MIN, Time.RTC_Min);
sil_wrw_mem((void *)RTC_HOUR, Time.RTC_Hour);
sil_wrw_mem((void *)RTC_DOM, Time.RTC_Mday);
sil_wrw_mem((void *)RTC_DOW, Time.RTC_Wday);
sil_wrw_mem((void *)RTC_DOY, Time.RTC_Yday);
sil_wrw_mem((void *)RTC_MONTH, Time.RTC_Mon);
sil_wrw_mem((void *)RTC_YEAR, Time.RTC_Year);
/*ctc start*/
sil_wrw_mem((void *)RTC_CCR,sil_rew_mem((void *)RTC_CCR)&(~(1<<1)));
return ERCD_OK;
}
