//print stats, uninitialize simulator components, and exit w/ exitcode
void exit_now(int exit_code)
{
//print simulation stats and SMT statistics
sim_print_stats(stderr);
smt_print_stats();
//un-initialize the simulator
sim_uninit();
//Various cleanup
if(sim_simout != NULL)
{
fclose(stderr);
}
if(sim_progout != NULL)
{
close(sim_progfd);
}
if(sim_progerr != NULL)
{
close(sim_progerrfd);
}
delete v_argv;
delete v_envp;
delete sim_odb;
delete sim_sdb;
//all done!
exit(exit_code);
}
/* print stats, uninitialize simulator components, and exit w/ exitcode */
static void
exit_now(int exit_code)
{
/* print simulation stats */
sim_print_stats(stderr);
/* un-initialize the simulator */
sim_uninit();
/* all done! */
exit(exit_code);
}
/* local machine state accessor */
static char * /* err str, NULL for no err */
cache_mstate_obj(FILE *stream, /* output stream */
char *cmd, /* optional command string */
struct regs_t *regs, /* register to access */
struct mem_t *mem) /* memory to access */
{
/* just dump intermediate stats */
sim_print_stats(stream);
/* no error */
return NULL;
}
/* print stats, uninitialize simulator components, and exit w/ exitcode */
static void
exit_now (int exit_code)
{
/* print simulation stats */
sim_print_stats (stderr);
/* un-initialize the simulator */
sim_uninit ();
if (exit_code)
fprintf (stderr, "error: some function call exit_now with exit_code %d\n", exit_code);
/* all done! */
exit (exit_code);
}
/* print stats, uninitialize simulator components, and exit w/ exitcode */
static void
exit_now(int exit_code, simoutorder *simobj)
{
/* print simulation stats */
sim_print_stats(stderr, simobj);
/* un-initialize the simulator */
simobj->sim_uninit();
/* all done! */
//exit(exit_code);
}
/* start simulation, program loaded, processor precise state initialized */
bool_t
sim_sample(unsigned int n_insn)
{
md_inst_t inst;
enum md_fault_t fault;
struct predec_insn_t *pdi;
counter_t sim_num_insn_begin = sim_num_insn;
bool_t fdumpinsn;
while (n_insn == 0 || sim_num_insn < sim_num_insn_begin + n_insn)
{
/* maintain $r0 semantics */
regs.regs[MD_REG_ZERO].q = 0;
regs.regs[MD_FREG_ZERO].d = 0.0;
/* get the next instruction to execute */
if (itlb)
cache_access(itlb, mc_READ, regs.PC, sizeof(md_inst_t), 0, NULL, tlb_miss_handler);
if (cache_il1)
cache_access(cache_il1, mc_READ, regs.PC, sizeof(md_inst_t), 0, NULL, l1_miss_handler);
mem_access(mem, mc_READ, regs.PC, &inst, sizeof(md_inst_t));
/* set default reference address and access mode */
regs.addr = 0; regs.dsize = 0;
/* set default fault - none */
fault = md_fault_none;
/* get the next instruction to execute */
pdi = predec_lookup(regs.PC);
if (!pdi)
{
mem_access(mem, mc_READ, regs.PC, &inst, sizeof(md_inst_t));
pdi = predec_enter(regs.PC, inst);
}
/* keep an instruction count */
if (pdi->iclass != ic_nop)
{
sim_num_insn++;
sim_sample_insn++;
sim_sample_insn_split[pdi->iclass]++;
}
fdumpinsn = fdump && sim_num_insn >= insn_dumpbegin && sim_num_insn < insn_dumpend;
inst = pdi->inst;
/* execute the instruction */
switch (pdi->poi.op)
{
#define DEFINST(OP,MSK,NAME,OPFORM,RES,FLAGS,O1,O2,I1,I2,I3) \
case OP: \
SYMCAT(OP,_IMPL); \
break;
#define DEFLINK(OP,MSK,NAME,MASK,SHIFT) \
case OP: \
panic("attempted to execute a linking opcode");
#define CONNECT(OP)
#define DECLARE_FAULT(FAULT) \
{ fault = (FAULT); break; }
#include "machine.def"
default:
panic("attempted to execute a bogus opcode");
}
if (fault != md_fault_none)
fatal("fault (%d) detected @ 0x%08p", fault, regs.PC);
if (pdi->iclass == ic_load || pdi->iclass == ic_store || pdi->iclass == ic_prefetch)
{
enum mem_cmd_t dl1_cmd = pdi->iclass == ic_store ? mc_WRITE : (pdi->iclass == ic_load ? mc_READ : mc_PREFETCH);
enum mem_cmd_t dtlb_cmd = (pdi->iclass == ic_store || pdi->iclass == ic_load) ? mc_READ : mc_PREFETCH;
bool_t miss_info[ct_NUM] = {FALSE, FALSE, FALSE, FALSE};
if (cache_dl1)
cache_access(cache_dl1, dl1_cmd, regs.addr, regs.dsize, 0, miss_info, l1_miss_handler);
if (dtlb)
cache_access(dtlb, dtlb_cmd, regs.addr, regs.dsize, 0, NULL, tlb_miss_handler);
}
/* go to the next instruction */
regs.PC = regs.NPC;
regs.NPC += sizeof(md_inst_t);
if (verbose)
{
myfprintf(stderr, "%10n [xor: 0x%08x] @ 0x%08p: ",
sim_num_insn, md_xor_regs(®s), regs.PC);
md_print_insn(inst, regs.PC, stderr);
if (MD_OP_HASFLAGS(pdi->poi.op, F_MEM))
myfprintf(stderr, " mem: 0x%08p", regs.addr);
fprintf(stderr, "\n");
/* fflush(stderr); */
}
if (fdumpinsn)
{
fprintf(fdump, "%-9u: 0x%08x ", (word_t)sim_num_insn, (word_t)regs.PC);
if (LREG_ISDEP(pdi->lregnums[DEP_O1]))
myfprintf(fdump, " O1: %016p", regs_value(pdi->lregnums[DEP_O1]));
fprintf(fdump, "\n");
}
if (fdump && sim_num_insn == insn_dumpend)
{
fflush(fdump);
fclose(fdump);
}
/* finish early? */
if (insn_limit && sim_sample_insn >= insn_limit)
{
myfprintf(stderr, "Reached instruction limit: %u\n", insn_limit);
return FALSE;
}
if (insn_progress && sim_sample_insn >= insn_progress)
{
sim_print_stats(stderr);
fflush(stderr);
while (sim_sample_insn >= insn_progress)
insn_progress += insn_progress_update;
}
}
return (sim_num_insn - sim_num_insn_begin == n_insn);
}
