void sim_reset()
{
if (!initialized)
sim_init();
clear_mem(reg);
minAddr = 0;
memCnt = 0;
#ifdef HAS_GUI
if (gui_mode) {
signal_register_clear();
create_memory_display(minAddr, memCnt);
sim_report();
}
#endif
if (plusmode) {
prev_icode = prev_icode_in = I_NOP;
prev_ifun = prev_ifun_in = 0;
prev_valc = prev_valc_in = 0;
prev_valm = prev_valm_in = 0;
prev_valp = prev_valp_in = 0;
prev_bcond = prev_bcond_in = FALSE;
pc = 0;
} else {
pc_in = 0;
}
cc = DEFAULT_CC;
cc_in = DEFAULT_CC;
destE = REG_NONE;
destM = REG_NONE;
mem_write = FALSE;
mem_addr = 0;
mem_data = 0;
/* Reset intermediate values to clear display */
icode = I_NOP;
ifun = 0;
instr = HPACK(I_NOP, F_NONE);
ra = REG_NONE;
rb = REG_NONE;
valc = 0;
valp = 0;
srcA = REG_NONE;
srcB = REG_NONE;
destE = REG_NONE;
destM = REG_NONE;
vala = 0;
valb = 0;
vale = 0;
cond = FALSE;
bcond = FALSE;
valm = 0;
sim_report();
}
void sim_reset()
{
if (!initialized)
sim_init();
clear_pipes();
clear_mem(reg);
minAddr = 0;
memCnt = 0;
starting_up = 1;
cycles = instructions = 0;
#ifdef HAS_GUI
if (gui_mode) {
signal_register_clear();
create_memory_display(minAddr, memCnt);
}
#endif
amux = bmux = MUX_NONE;
cc = cc_in = DEFAULT_CC;
wb_destE = REG_NONE;
wb_valE = 0;
wb_destM = REG_NONE;
wb_valM = 0;
mem_addr = 0;
mem_data = 0;
mem_write = FALSE;
sim_report();
}
/* Max_instr indicates maximum number of instructions that
want to complete during this simulation run. */
static exc_t sim_step_pipe(int max_instr)
{
exc_t wb_exc = mem_wb_curr->exception;
exc_t mem_exc = mem_wb_next->exception;
/* How many instructions are ahead of one in wb / ex? */
int ahead_mem = (wb_exc != EXC_BUBBLE);
int ahead_ex = ahead_mem + (mem_exc != EXC_BUBBLE);
bool_t wb_ok = (wb_exc == EXC_NONE) || (wb_exc == EXC_BUBBLE);
bool_t mem_ok = (mem_exc == EXC_NONE) || (mem_exc == EXC_BUBBLE);
bool_t update_mem = wb_ok && ahead_mem < max_instr;
bool_t update_cc = update_mem && mem_ok && ahead_ex < max_instr;
if (!update_mem) {
sim_log("Disabling memory write. wb_exc = %s\n", exc_name(wb_exc));
}
/* Update program-visible state */
update_state(update_mem, update_cc);
/* Update pipe registers */
update_pipes();
if (pc_state->op == P_ERROR)
pc_curr->exception = EXC_PIPE;
if (if_id_state->op == P_ERROR)
if_id_curr->exception = EXC_PIPE;
if (id_ex_state->op == P_ERROR)
id_ex_curr->exception = EXC_PIPE;
if (ex_mem_state->op == P_ERROR)
ex_mem_curr->exception = EXC_PIPE;
if (mem_wb_state->op == P_ERROR)
mem_wb_curr->exception = EXC_PIPE;
/* Need to do decode after execute & memory stages,
and memory stage before execute, in order to propagate
forwarding values properly */
do_if_stage();
do_mem_stage();
do_ex_stage();
do_id_wb_stages();
do_stall_check();
if (id_ex_curr->exception != EXC_NONE
&& id_ex_curr->exception != EXC_BUBBLE) {
if_id_state->op = P_BUBBLE;
id_ex_state->op = P_BUBBLE;
}
/* Performance monitoring */
if (mem_wb_curr->exception != EXC_BUBBLE && mem_wb_curr->icode != I_POP2) {
starting_up = 0;
instructions++;
cycles++;
} else {
if (!starting_up)
cycles++;
}
sim_report();
return mem_wb_curr->exception;
}
/* Max_instr indicates maximum number of instructions that
want to complete during this simulation run. */
static byte_t sim_step_pipe(int max_instr, int ccount)
{
byte_t wb_status = mem_wb_curr->status;
byte_t mem_status = mem_wb_next->status;
/* How many instructions are ahead of one in wb / ex? */
int ahead_mem = (wb_status != STAT_BUB);
int ahead_ex = ahead_mem + (mem_status != STAT_BUB);
bool_t update_mem = ahead_mem < max_instr;
bool_t update_cc = ahead_ex < max_instr;
/* Update program-visible state */
update_state(update_mem, update_cc);
/* Update pipe registers */
update_pipes();
tty_report(ccount);
if (pc_state->op == P_ERROR)
pc_curr->status = STAT_PIP;
if (if_id_state->op == P_ERROR)
if_id_curr->status = STAT_PIP;
if (id_ex_state->op == P_ERROR)
id_ex_curr->status = STAT_PIP;
if (ex_mem_state->op == P_ERROR)
ex_mem_curr->status = STAT_PIP;
if (mem_wb_state->op == P_ERROR)
mem_wb_curr->status = STAT_PIP;
/* Need to do decode after execute & memory stages,
and memory stage before execute, in order to propagate
forwarding values properly */
do_if_stage();
do_mem_stage();
do_ex_stage();
do_id_wb_stages();
do_stall_check();
#if 0
/* This doesn't seem necessary */
if (id_ex_curr->status != STAT_AOK
&& id_ex_curr->status != STAT_BUB) {
if_id_state->op = P_BUBBLE;
id_ex_state->op = P_BUBBLE;
}
#endif
/* Performance monitoring */
if (mem_wb_curr->status != STAT_BUB) {
//if (mem_wb_curr->status != STAT_BUB && mem_wb_curr->icode != I_POP2) {
starting_up = 0;
instructions++;
cycles++;
} else {
if (!starting_up)
cycles++;
}
sim_report();
return status;
}
void sim_reset()
{
if (!initialized)
sim_init();
clear_pipes();
clear_reg(reg);
minAddr = 0;
memCnt = 0;
starting_up = 1;
cycles = instructions = 0;
cc = DEFAULT_CC;
status = STAT_AOK;
amux = bmux = MUX_NONE;
cc = cc_in = DEFAULT_CC;
wb_destE = REG_NONE;
wb_valE = 0;
wb_destM = REG_NONE;
wb_valM = 0;
mem_addr = 0;
mem_data = 0;
mem_write = FALSE;
sim_report();
}
/* Return resulting exception status */
static exc_t sim_step()
{
word_t aluA;
word_t aluB;
word_t alufun;
exc_t status = update_state(); /* Update state from last cycle */
if (plusmode) {
pc = gen_pc();
}
valp = pc;
if (get_byte_val(mem, valp, &instr)) {
icode = HI4(instr);
ifun = LO4(instr);
} else {
instr = HPACK(I_NOP,0);
icode = I_NOP;
ifun = 0;
status = EXC_ADDR;
sim_log("Couldn't fetch at address 0x%x\n", valp);
}
valp++;
if (gen_need_regids()) {
byte_t regids;
if (get_byte_val(mem, valp, ®ids)) {
ra = GET_RA(regids);
rb = GET_RB(regids);
} else {
ra = REG_NONE;
rb = REG_NONE;
status = EXC_ADDR;
sim_log("Couldn't fetch at address 0x%x\n", valp);
}
valp++;
} else {
ra = REG_NONE;
rb = REG_NONE;
}
if (gen_need_valC()) {
if (get_word_val(mem, valp, &valc)) {
} else {
valc = 0;
status = EXC_ADDR;
sim_log("Couldn't fetch at address 0x%x\n", valp);
}
valp+=4;
} else {
valc = 0;
}
if (status == EXC_NONE && !gen_instr_valid()) {
status = EXC_INSTR;
}
sim_log("IF: Fetched %s at 0x%x. ra=%s, rb=%s, valC = 0x%x\n",
iname(HPACK(icode,ifun)), pc, reg_name(ra), reg_name(rb), valc);
if (status == EXC_NONE && icode == I_HALT) {
status = EXC_HALT;
}
srcA = gen_srcA();
if (srcA != REG_NONE) {
vala = get_reg_val(reg, srcA);
} else {
vala = 0;
}
srcB = gen_srcB();
if (srcB != REG_NONE) {
valb = get_reg_val(reg, srcB);
} else {
valb = 0;
}
destE = gen_dstE();
destM = gen_dstM();
aluA = gen_aluA();
aluB = gen_aluB();
alufun = gen_alufun();
vale = compute_alu(alufun, aluA, aluB);
cc_in = cc;
if (gen_set_cc())
cc_in = compute_cc(alufun, aluA, aluB);
bcond = (icode == I_JMP) && take_branch(cc, ifun);
mem_addr = gen_mem_addr();
mem_data = gen_mem_data();
if (status == EXC_NONE && gen_mem_read()) {
if (!get_word_val(mem, mem_addr, &valm)) {
sim_log("Couldn't read at address 0x%x\n", mem_addr);
return EXC_ADDR;
}
} else
valm = 0;
mem_write = status == EXC_NONE && gen_mem_write();
if (plusmode) {
prev_icode_in = icode;
prev_ifun_in = ifun;
prev_valc_in = valc;
prev_valm_in = valm;
prev_valp_in = valp;
prev_bcond_in = bcond;
} else {
/* Update PC */
pc_in = gen_new_pc();
}
sim_report();
return status;
}
/* Return resulting status */
static byte_t sim_step()
{
word_t aluA;
word_t aluB;
word_t alufun;
status = STAT_AOK;
imem_error = dmem_error = FALSE;
update_state(); /* Update state from last cycle */
if (plusmode) {
pc = gen_pc();
}
valp = pc;
instr = HPACK(I_NOP, F_NONE);
imem_error = !get_byte_val(mem, valp, &instr);
if (imem_error) {
sim_log("Couldn't fetch at address 0x%x\n", valp);
}
imem_icode = HI4(instr);
imem_ifun = LO4(instr);
icode = gen_icode();
ifun = gen_ifun();
instr_valid = gen_instr_valid();
valp++;
if (gen_need_regids()) {
byte_t regids;
if (get_byte_val(mem, valp, ®ids)) {
ra = GET_RA(regids);
rb = GET_RB(regids);
} else {
ra = REG_NONE;
rb = REG_NONE;
status = STAT_ADR;
sim_log("Couldn't fetch at address 0x%x\n", valp);
}
valp++;
} else {
ra = REG_NONE;
rb = REG_NONE;
}
if (gen_need_valC()) {
if (get_word_val(mem, valp, &valc)) {
} else {
valc = 0;
status = STAT_ADR;
sim_log("Couldn't fetch at address 0x%x\n", valp);
}
valp+=4;
} else {
valc = 0;
}
sim_log("IF: Fetched %s at 0x%x. ra=%s, rb=%s, valC = 0x%x\n",
iname(HPACK(icode,ifun)), pc, reg_name(ra), reg_name(rb), valc);
if (status == STAT_AOK && icode == I_HALT) {
status = STAT_HLT;
}
srcA = gen_srcA();
if (srcA != REG_NONE) {
vala = get_reg_val(reg, srcA);
} else {
vala = 0;
}
srcB = gen_srcB();
if (srcB != REG_NONE) {
valb = get_reg_val(reg, srcB);
} else {
valb = 0;
}
cond = cond_holds(cc, ifun);
destE = gen_dstE();
destM = gen_dstM();
aluA = gen_aluA();
aluB = gen_aluB();
alufun = gen_alufun();
vale = compute_alu(alufun, aluA, aluB);
cc_in = cc;
if (gen_set_cc())
cc_in = compute_cc(alufun, aluA, aluB);
bcond = cond && (icode == I_JMP);
mem_addr = gen_mem_addr();
mem_data = gen_mem_data();
if (gen_mem_read()) {
dmem_error = dmem_error || !get_word_val(mem, mem_addr, &valm);
if (dmem_error) {
sim_log("Couldn't read at address 0x%x\n", mem_addr);
}
} else
valm = 0;
mem_write = gen_mem_write();
if (mem_write) {
/* Do a test read of the data memory to make sure address is OK */
word_t junk;
dmem_error = dmem_error || !get_word_val(mem, mem_addr, &junk);
}
status = gen_Stat();
if (plusmode) {
prev_icode_in = icode;
prev_ifun_in = ifun;
prev_valc_in = valc;
prev_valm_in = valm;
prev_valp_in = valp;
prev_bcond_in = bcond;
} else {
/* Update PC */
pc_in = gen_new_pc();
}
sim_report();
return status;
}
