Ejemplo n.º 1
0
static int slp_suspend_ops_enter(suspend_state_t state)
{
    /* legacy log */
    slp_notice("@@@@@@@@@@@@@@@@@@@@\n");
    slp_crit2("Chip_pm_enter\n");
    slp_notice("@@@@@@@@@@@@@@@@@@@@\n");

    if (slp_dump_gpio)
        gpio_dump_regs();

    if (slp_dump_regs)
        slp_dump_pm_regs();

    if (!spm_cpusys_can_power_down()) {
        slp_error("CANNOT SLEEP DUE TO CPU1/2/3 PON\n");
        return -EPERM;
    }

    if (slp_infra_pdn && !slp_cpu_pdn) {
        slp_error("CANNOT SLEEP DUE TO INFRA PDN BUT CPU PON\n");
        return -EPERM;
    }

#if SLP_SLEEP_DPIDLE_EN
    if (slp_ck26m_on)
        slp_wake_reason = spm_go_to_sleep_dpidle(slp_cpu_pdn, 0);
    else
#endif
        slp_wake_reason = spm_go_to_sleep(slp_cpu_pdn, slp_infra_pdn);

    return 0;
}
Ejemplo n.º 2
0
void mt6575_sleep(u32 timeout, kal_bool en_deep_idle)
{
    unsigned int topmisc, pdn0;
    
    printf("enter mt6575_sleep, timeout = %d\n", timeout);
    
    #if MT6575_SC_DEBUG
        slp_dump_pm_regs();
    #endif
    
    pdn0 = DRV_Reg32(PERI_GLOBALCON_PDN0);
    if (get_chip_eco_ver() == CHIP_E1) {
        /* power on UART0/1/2/3 to workaround handshake mode issue */
        DRV_WriteReg32(PERI_GLOBALCON_PDN0, pdn0 & ~(0xf << 24));
    }
    
    /* keep CA9 clock when entering WFI mode in sleep */
    topmisc = DRV_Reg32(TOP_MISC);
    DRV_WriteReg32(TOP_MISC, topmisc & ~(1U << 0));
    
    if (get_chip_eco_ver() != CHIP_E1) {
        if (en_deep_idle) {
            DRV_WriteReg32(TOPCKGEN_CON3, DRV_Reg32(TOPCKGEN_CON3) & 0x7FFF);
            DRV_WriteReg32(MDPLL_CON0, DRV_Reg32(MDPLL_CON0) | 0x1);
        }
    }
    
    rtc_writeif_lock();
    
    sc_go_to_sleep(timeout, en_deep_idle);
    
    rtc_writeif_unlock();
    
    if (get_chip_eco_ver() != CHIP_E1) {
        if (en_deep_idle) {
            DRV_WriteReg32(MDPLL_CON0, DRV_Reg32(MDPLL_CON0) & 0xFFFE);
            udelay(20);
            DRV_WriteReg32(TOPCKGEN_CON3, DRV_Reg32(TOPCKGEN_CON3) | 0x8000);
        }
    }
    
    /* restore TOP_MISC (and PERI_GLOBALCON_PDN0) */
    DRV_WriteReg32(TOP_MISC, topmisc);
    
    if (get_chip_eco_ver() == CHIP_E1)
        DRV_WriteReg32(PERI_GLOBALCON_PDN0, pdn0);
    
    return 0;
}
Ejemplo n.º 3
0
static int slp_suspend_ops_enter(suspend_state_t state)
{
#ifdef CONFIG_MTKPASR
    /* PASR SW operations */
    if (enter_pasrdpd())
	    goto pending_wakeup;
#endif

    /* legacy log */
    slp_notice("@@@@@@@@@@@@@@@@@@@@\n");
    slp_crit2("Chip_pm_enter\n");
    slp_notice("@@@@@@@@@@@@@@@@@@@@\n");

    if (slp_dump_gpio)
        gpio_dump_regs();

    if (slp_dump_regs)
        slp_dump_pm_regs();

    if (!spm_cpusys0_can_power_down()) {
        slp_error("CANNOT SLEEP DUE TO CPU1/2/3 PON\n");
        return -EPERM;
    }

    if (slp_infra_pdn && !slp_cpu_pdn) {
        slp_error("CANNOT SLEEP DUE TO INFRA PDN BUT CPU PON\n");
        return -EPERM;
    }

#if SLP_SLEEP_DPIDLE_EN
    if (slp_ck26m_on)
        slp_wake_reason = spm_go_to_sleep_dpidle(slp_cpu_pdn, slp_pwrlevel, slp_pwake_time);
    else
#endif
        slp_wake_reason = spm_go_to_sleep(slp_cpu_pdn, slp_infra_pdn, slp_pwake_time);

#ifdef CONFIG_MTKPASR
    /* PASR SW operations */
    leave_pasrdpd();
pending_wakeup:
#endif

    return 0;
}
Ejemplo n.º 4
0
static int slp_suspend_ops_enter(suspend_state_t state)
{
	u32 topmisc;
	unsigned int pwrlevel;

	/* legacy log */
	aee_sram_printk("_Chip_pm_enter\n");
	slp_xinfo("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n");
	slp_xinfo("_Chip_pm_enter @@@@@@@@@@@@@@@@@@@@@@\n");
	slp_xinfo(" @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n");

	if (slp_dump_gpio)
		gpio_dump_regs();

	/* keep CA9 clock frequency when WFI to sleep */
	topmisc = slp_read32(TOP_MISC);
	slp_write32(TOP_MISC, topmisc & ~(1U << 0));
	slp_write_sync();

	if (slp_dump_regs)
		slp_dump_pm_regs();

	rtc_disable_writeif();

	pwrlevel = slp_pwr_level;
	if ((pwrlevel != 0) && (slp_read32(0xf0009024) & 0x8000)) {
		slp_xerror("!!! WILL NOT POWER DOWN CPUSYS DUE TO CPU1 ON !!!\n");
		pwrlevel = 0;
	}
	slp_wake_reason = sc_go_to_sleep(pwrlevel);

	rtc_enable_writeif();

	/* restore TOP_MISC */
	slp_write32(TOP_MISC, topmisc);
	slp_write_sync();

	return 0;
}
Ejemplo n.º 5
0
static int slp_suspend_ops_enter(suspend_state_t state)
{
    int ret = 0;

#ifdef CONFIG_MTK_TC1_FM_AT_SUSPEND
    int fm_radio_is_playing = 0;
    if ( ConditionEnterSuspend() == true )
    	fm_radio_is_playing = 0;
    else
    	fm_radio_is_playing = 1;
#endif /* CONFIG_MTK_TC1_FM_AT_SUSPEND */ 
#ifdef CONFIG_MTKPASR
    /* PASR SW operations */
    enter_pasrdpd();
#endif

    /* legacy log */
    slp_notice("@@@@@@@@@@@@@@@@@@@@\n");
    slp_crit2("Chip_pm_enter\n");
    slp_notice("@@@@@@@@@@@@@@@@@@@@\n");

//FIXME: for K2 bring up
    if (slp_dump_gpio)
        gpio_dump_regs();
#if 0
    if (slp_dump_regs)
        slp_dump_pm_regs();
#endif

    if (slp_check_mtcmos_pll)
        slp_check_pm_mtcmos_pll();

    if (!spm_cpusys0_can_power_down()) {
        slp_error("CANNOT SLEEP DUE TO CPU1~x PON, SPM_PWR_STATUS = 0x%x, SPM_PWR_STATUS_2ND = 0x%x\n",
                  slp_read(SPM_PWR_STATUS), slp_read(SPM_PWR_STATUS_2ND));
        //return -EPERM;
        ret = -EPERM;
        goto LEAVE_SLEEP;
    }

    if (is_infra_pdn(slp_spm_flags) && !is_cpu_pdn(slp_spm_flags)) {
        slp_error("CANNOT SLEEP DUE TO INFRA PDN BUT CPU PON\n");
        //return -EPERM;
        ret = -EPERM;
        goto LEAVE_SLEEP;
    }

    
    /* only for test */
    #if 0
    slp_pasr_en(1, 0x0);
    slp_dpd_en(1);
    #endif

#if SLP_SLEEP_DPIDLE_EN
#ifdef CONFIG_MTK_TC1_FM_AT_SUSPEND
    if (slp_ck26m_on | fm_radio_is_playing)
#else
    if (slp_ck26m_on)
#endif
        slp_wake_reason = spm_go_to_sleep_dpidle(slp_spm_deepidle_flags, slp_spm_data);
    else
#endif
        slp_wake_reason = spm_go_to_sleep(slp_spm_flags, slp_spm_data);

LEAVE_SLEEP:
#ifdef CONFIG_MTKPASR
    /* PASR SW operations */
    leave_pasrdpd();
#endif

#ifdef CONFIG_MTK_SYSTRACKER
    systracker_enable();
#endif

    return ret;
}