/**
* \brief Test SPI setting.
*
* This test tests SPI reset/enable/disable.
*
* \param test Current test case.
*/
static void run_spi_ctrl_test(const struct test_case *test)
{
spi_enable_clock(CONF_TEST_SPI);
/* Test enable */
spi_enable(CONF_TEST_SPI);
test_assert_true(test, spi_is_enabled(CONF_TEST_SPI),
"Test SPI enable: enable failed");
/* Test reset */
spi_reset(CONF_TEST_SPI);
test_assert_true(test,
!spi_is_enabled(CONF_TEST_SPI) &&
CONF_TEST_SPI->SPI_MR == 0 &&
CONF_TEST_SPI->SPI_IMR == 0 &&
CONF_TEST_SPI->SPI_CSR[0] == 0 &&
CONF_TEST_SPI->SPI_CSR[1] == 0 &&
CONF_TEST_SPI->SPI_CSR[2] == 0 &&
CONF_TEST_SPI->SPI_CSR[3] == 0 &&
#if SAM4L
CONF_TEST_SPI->SPI_WPCR == 0,
#else
CONF_TEST_SPI->SPI_WPMR == 0,
#endif
"Test SPI reset: should have read 0");
}
void sd_mmc_spi_init(void)
{
sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
// Initialize SPI interface and enable it
#if defined(SD_MMC_SPI_USES_USART_SPI_SERVICE)
usart_spi_init(SD_MMC_SPI);
#else
if (!spi_is_enabled(SD_MMC_SPI)) {
spi_master_init(SD_MMC_SPI);
spi_enable(SD_MMC_SPI);
}
#endif
}
spi_p spi_new_instance(Spi * spi_base, uint8_t spi_chip_sel, uint32_t spi_freq, uint8_t spi_mode, uint8_t buffer_size, void(*handler_call_back )(spi_p, uint8_t))
{
_spi_base = spi_base;
if (!spi_is_enabled(_spi_base)) {
_spi_init_base(spi_base);
}
spi_p _spi = malloc(sizeof *_spi);
_spi->_call_back = handler_call_back;
_spi->_cs_pin = spi_chip_sel;
_spi->_spi_rx_fifo_desc = (fifo_desc_t *)malloc(sizeof(fifo_desc_t));
_spi->_spi_tx_fifo_desc = (fifo_desc_t *)malloc(sizeof(fifo_desc_t));
union spi_buffer_element *spi_tx_fifo_buffer = (union spi_buffer_element *)(malloc(sizeof(union spi_buffer_element) * buffer_size));
union spi_buffer_element *spi_rx_fifo_buffer = (union spi_buffer_element *)(malloc(sizeof(union spi_buffer_element) * buffer_size));
fifo_init(_spi->_spi_rx_fifo_desc, spi_rx_fifo_buffer, buffer_size);
fifo_init(_spi->_spi_tx_fifo_desc, spi_tx_fifo_buffer, buffer_size);
spi_set_peripheral_chip_select_value(spi_base, spi_get_pcs(spi_chip_sel));
switch (spi_mode)
{
case 0:
spi_set_clock_polarity(spi_base, spi_chip_sel,0);
spi_set_clock_phase(spi_base, spi_chip_sel, 1);
break;
case 1:
spi_set_clock_polarity(spi_base, spi_chip_sel, 0);
spi_set_clock_phase(spi_base, spi_chip_sel, 0);
break;
case 2:
spi_set_clock_polarity(spi_base, spi_chip_sel, 1);
spi_set_clock_phase(spi_base, spi_chip_sel, 1);
break;
case 3:
spi_set_clock_polarity(spi_base, spi_chip_sel, 1);
spi_set_clock_phase(spi_base, spi_chip_sel, 0);
break;
}
spi_set_bits_per_transfer(spi_base, spi_chip_sel, SPI_CSR_BITS_8_BIT);
spi_configure_cs_behavior(spi_base, spi_chip_sel, SPI_CS_KEEP_LOW);
spi_set_baudrate_div(spi_base, spi_chip_sel, (sysclk_get_peripheral_hz() / spi_freq));
spi_set_delay_between_chip_select(spi_base, 0x10);
spi_set_transfer_delay(spi_base, spi_chip_sel, 0x01, 0x10);
spi_enable(spi_base);
return _spi;
}
void memories_initialization(void)
{
//-- Hmatrix bus configuration
// This improve speed performance
#ifdef AVR32_HMATRIXB
union {
unsigned long scfg;
avr32_hmatrixb_scfg_t SCFG;
} u_avr32_hmatrixb_scfg;
sysclk_enable_pbb_module(SYSCLK_HMATRIX);
// For the internal-flash HMATRIX slave, use last master as default.
u_avr32_hmatrixb_scfg.scfg =
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_FLASH];
u_avr32_hmatrixb_scfg.SCFG.defmstr_type =
AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_FLASH] =
u_avr32_hmatrixb_scfg.scfg;
// For the internal-SRAM HMATRIX slave, use last master as default.
u_avr32_hmatrixb_scfg.scfg =
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_SRAM];
u_avr32_hmatrixb_scfg.SCFG.defmstr_type =
AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_SRAM] =
u_avr32_hmatrixb_scfg.scfg;
# ifdef AVR32_HMATRIXB_SLAVE_EBI
// For the EBI HMATRIX slave, use last master as default.
u_avr32_hmatrixb_scfg.scfg =
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_EBI];
u_avr32_hmatrixb_scfg.SCFG.defmstr_type =
AVR32_HMATRIXB_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIXB.scfg[AVR32_HMATRIXB_SLAVE_EBI] =
u_avr32_hmatrixb_scfg.scfg;
# endif
#endif
#ifdef AVR32_HMATRIX
union {
unsigned long scfg;
avr32_hmatrix_scfg_t SCFG;
} u_avr32_hmatrix_scfg;
sysclk_enable_pbb_module(SYSCLK_HMATRIX);
// For the internal-flash HMATRIX slave, use last master as default.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH];
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_FLASH] =
u_avr32_hmatrix_scfg.scfg;
// For the internal-SRAM HMATRIX slave, use last master as default.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_SRAM];
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_SRAM] =
u_avr32_hmatrix_scfg.scfg;
# ifdef AVR32_HMATRIX_SLAVE_EBI
// For the EBI HMATRIX slave, use last master as default.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_EBI];
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_EBI] =
u_avr32_hmatrix_scfg.scfg;
# endif
#endif
#ifdef AVR32_HMATRIX_MASTER_USBB_DMA
union {
unsigned long mcfg;
avr32_hmatrix_mcfg_t MCFG;
} u_avr32_hmatrix_mcfg;
// For the USBB DMA HMATRIX master, use infinite length burst.
u_avr32_hmatrix_mcfg.mcfg =
AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_USBB_DMA];
u_avr32_hmatrix_mcfg.MCFG.ulbt =
AVR32_HMATRIX_ULBT_INFINITE;
AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_USBB_DMA] =
u_avr32_hmatrix_mcfg.mcfg;
// For the USBB DPRAM HMATRIX slave, use the USBB DMA as fixed default master.
u_avr32_hmatrix_scfg.scfg =
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_USBB_DPRAM];
u_avr32_hmatrix_scfg.SCFG.fixed_defmstr =
AVR32_HMATRIX_MASTER_USBB_DMA;
u_avr32_hmatrix_scfg.SCFG.defmstr_type =
AVR32_HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT;
AVR32_HMATRIX.scfg[AVR32_HMATRIX_SLAVE_USBB_DPRAM] =
u_avr32_hmatrix_scfg.scfg;
#endif
#if (defined AT45DBX_MEM) && (AT45DBX_MEM == ENABLE)
sysclk_enable_peripheral_clock(AT45DBX_SPI_MODULE);
at45dbx_init();
#endif
#if ((defined SD_MMC_MCI_0_MEM) && (SD_MMC_MCI_0_MEM == ENABLE)) \
|| ((defined SD_MMC_MCI_1_MEM) && (SD_MMC_MCI_1_MEM == ENABLE))
sysclk_enable_pbb_module(SYSCLK_MCI);
sysclk_enable_hsb_module(SYSCLK_DMACA);
sd_mmc_mci_init(SD_SLOT_8BITS, sysclk_get_pbb_hz(), sysclk_get_cpu_hz());
#endif
#if (defined SD_MMC_SPI_MEM) && (SD_MMC_SPI_MEM == ENABLE)
// SPI options.
spi_options_t spiOptions = {
.reg = SD_MMC_SPI_NPCS,
.baudrate = SD_MMC_SPI_MASTER_SPEED, // Defined in conf_sd_mmc_spi.h.
.bits = SD_MMC_SPI_BITS, // Defined in conf_sd_mmc_spi.h.
.spck_delay = 0,
.trans_delay = 0,
.stay_act = 1,
.spi_mode = 0,
.modfdis = 1
};
sysclk_enable_peripheral_clock(SD_MMC_SPI);
// If the SPI used by the SD/MMC is not enabled.
if (!spi_is_enabled(SD_MMC_SPI)) {
// Initialize as master.
spi_initMaster(SD_MMC_SPI, &spiOptions);
// Set selection mode: variable_ps, pcs_decode, delay.
spi_selectionMode(SD_MMC_SPI, 0, 0, 0);
// Enable SPI.
spi_enable(SD_MMC_SPI);
}
// Initialize SD/MMC with SPI PB clock.
sd_mmc_spi_init(spiOptions,sysclk_get_pba_hz());
#endif // SD_MMC_SPI_MEM == ENABLE
}
