void at45db041b_read_data(u16_t page,
u16_t start_byte_in_page,
u8_t *buffer,
u16_t number_of_bytes)
{
// Wait until Flash is not busy
while(!at45db041b_ready())
{
;
}
// Select serial Flash
AT45DB041B_CS_LO();
// Send command
spi_tx_byte(AT45DB041B_CMD_CONTINUOUS_ARRAY_READ);
// Send address
spi_tx_byte((page>>7)&0xFF);
spi_tx_byte(((page<<1)|(start_byte_in_page>>8))&0xFF);
spi_tx_byte(start_byte_in_page&0xFF);
// Send dont-care bits
spi_tx_byte(0x00);
spi_tx_byte(0x00);
spi_tx_byte(0x00);
spi_tx_byte(0x00);
// Read data
spi_rx_data(buffer, number_of_bytes);
// Deselect serial Flash
AT45DB041B_CS_HI();
}
void at45db041b_read_page(u16_t page, u8_t* buffer)
{
// Wait until Flash is not busy
while(!at45db041b_ready())
{
;
}
// Select serial Flash
AT45DB041B_CS_LO();
// Send command
spi_tx_byte(AT45DB041B_CMD_MAIN_MEMORY_PAGE_READ);
// Send address
spi_tx_byte((u8_t)(page>>7)&0xFF);
spi_tx_byte((u8_t)(page<<1)&0xFF);
spi_tx_byte(0x00);
// Send dont-care bits
spi_tx_byte(0x00);
spi_tx_byte(0x00);
spi_tx_byte(0x00);
spi_tx_byte(0x00);
// Read data
spi_rx_data(buffer, AT45DB041B_PAGE_SIZE);
// Deselect serial Flash
AT45DB041B_CS_HI();
}
/**
****************************************************************************************
* @brief SPI0 RX interrupt handler.
* @description
* If SPI0 RX FIFO is not empty, it then generates interrupt. In this handler, data is received from
* port SPI0 until expected receiving data size is reduced to zero. After last data received, the callback function is called.
****************************************************************************************
*/
void SPI0_IRQHandler(void)
{
#if (CONFIG_SPI0_RX_ENABLE_INTERRUPT==TRUE)
while ( spi_spi_GetSR(QN_SPI0) & SPI_MASK_RX_FIFO_NEMT_IF ) { // RX FIFO not empty interrupt
if (spi0_env.rx.size > 0) {
spi_rx_data(QN_SPI0, (struct spi_env_tag *)&spi0_env);
if (spi0_env.rx.size <= 0) {
// Disable RX interrupt
spi_int_enable(QN_SPI0, SPI_RX_INT, MASK_DISABLE);
#if SPI_CALLBACK_EN==TRUE
// Call end of reception callback
if (spi0_env.rx.callback != NULL)
{
spi0_env.rx.callback();
}
#endif
}
}
else {
spi_spi_GetRXD(QN_SPI0); // clear interrupt
}
}
#endif
if ( spi_spi_GetSR(QN_SPI0) & SPI_MASK_TX_FIFO_NFUL_IF ) /* TX FIFO not full interrupt */
{
#if (CONFIG_SPI0_TX_ENABLE_INTERRUPT==TRUE)
if (spi0_env.tx.size > 0) {
spi_tx_data(QN_SPI0, (struct spi_env_tag *)&spi0_env);
NVIC_ClearPendingIRQ(SPI0_TX_IRQn);
if (spi0_env.tx.size <= 0) {
// Disable TX interrupt
spi_int_enable(QN_SPI0, SPI_TX_INT, MASK_DISABLE);
#if SPI_CALLBACK_EN==TRUE
// Call end of transmission callback
if (spi0_env.tx.callback != NULL)
{
spi0_env.tx.callback();
}
#endif
}
}
else
#endif
{
if ( (spi0_env.mode == SPI_MASTER_MOD)
&& (spi0_env.rx.size > 0) ) {
#if (CONFIG_SPI0_TX_ENABLE_INTERRUPT==FALSE)
if (spi_check_tx_free(QN_SPI0) == SPI_TX_FREE)
#endif
spi_spi_SetTXD(QN_SPI0, SPI_DUMMY_DATA);
}
}
}
}
static void spi_receive_data(QN_SPI_TypeDef * SPI, struct spi_env_tag *spi_env)
{
while ( spi_env->rx.size > 0 )
{
/* As long as Receive FIFO is not empty, we can always receive. */
/* if it's a peer-to-peer communication, TXD needs to be written before a read can take place. */
if ( (spi_env->mode == SPI_MASTER_MOD) && (spi_check_tx_free(SPI) == SPI_TX_FREE) ) {
spi_spi_SetTXD(SPI, SPI_DUMMY_DATA);
/* Wait until the Busy bit is cleared */
//while ( spi_spi_GetSR(SPI) & SPI_MASK_BUSY );
}
while ( !(spi_spi_GetSR(SPI) & SPI_MASK_RX_FIFO_NEMT_IF) );
spi_rx_data(SPI, spi_env);
}
#if SPI_CALLBACK_EN==TRUE
// Call end of reception callback
if(spi_env->rx.callback != NULL)
{
spi_env->rx.callback();
}
#endif
}
