void spi_set_speed(spi_speed_t speed) {
if (speed == SPI_SPEED_FAST) {
spi_set_divisor(SPI_DIVISOR_FAST);
} else {
spi_set_divisor(SPI_DIVISOR_SLOW);
}
}
int do_sd_initialize (sd_context_t *sdc)
{
/* Initialize the SPI controller */
spi_initialize();
/* Set the maximum SPI clock rate possible */
spi_set_divisor(PERIPH_CLOCKRATE/400000);
/* Initialization OK? */
if (sd_initialize(sdc) != 1)
return 0;
spi_set_divisor(2); //---- 2011 0905 spi full speed
return 1;
}
int do_sd_initialize (void) {
/* Initialize and enable the SPI module */
P1SEL = 0x00E; // Setup P1 for SPI mode
P1OUT |= 0x000; // Setup P3.4 as the SS signal, active low. So, initialize it high.
P1DIR |= 0x000; // Set up P3.4 as an output
U0CTL = (CHAR | SYNC | MM | SWRST); // 8-bit, SPI, Master
U0TCTL = (SSEL1 | STC | CKPH); // Normal polarity, 3-wire
U0BR0 = 0x002; // SPICLK = SMCLK/2 (2=Minimum divisor)
U0BR1 = 0x000;
U0MCTL = 0x000;
ME1 |= USPIE0; // Module enable
U0CTL &= ~SWRST; // SPI enable
/* Set the baud-rate divisor. The correct value is computed by dividing
the clock rate by the desired baud rate. The minimum divisor allowed
is 2. */
U0CTL |= SWRST; // Temporarily disable the SPI module
U0BR1 = (PERIPH_CLOCKRATE/400000) >> 8;
U0BR0 = (PERIPH_CLOCKRATE/400000);
U0CTL &= ~SWRST; // Re-enable SPI
/* Initialization OK? */
if (sd_initialize() != 1)
return 0;
/* Set the maximum SPI clock rate possible */
spi_set_divisor(2);
return 1;
}
void spi_init(spi_speed_t speed) {
/* set up SPI I/O pins */
SPI_PORT = (SPI_PORT & ~SPI_MASK) | SPI_SCK | SPI_SS | SPI_MISO;
SPI_DDR = (SPI_DDR & ~SPI_MASK) | SPI_SCK | SPI_SS | SPI_MOSI;
/* enable and initialize SPI */
if (speed == SPI_SPEED_FAST) {
spi_set_divisor(SPI_DIVISOR_FAST);
} else {
spi_set_divisor(SPI_DIVISOR_SLOW);
}
/* Clear buffers, just to be sure */
(void) SPSR;
(void) SPDR;
}
