static uint8_t sd_write_block(uint32_t block, uint8_t *buf)
{
int32_t i;
uint8_t res;
spi_start();
while (sd_command(WRITE_SINGLE_BLOCK, block) != 0x00);
spi_sendrecv(0xfe);
for (i = 0; i < 512; i++)
spi_sendrecv(buf[i]);
spi_sendrecv(0xff);
spi_sendrecv(0xff);
res = spi_sendrecv(0xff);
if ((res & 0x1f) != 0x05) { //res = 0bXXX0AAA1 ; AAA='010' - data accepted
spi_stop(); //AAA='101' - CRC error
//AAA='110' - write error
return res;
}
while (!spi_sendrecv(0xff));
spi_stop();
spi_sendrecv(0xff);
spi_start();
while (!spi_sendrecv(0xff));
spi_stop();
return 0;
}
void spi_read(uint8_t addr , uint8_t *data, uint8_t len)
{
uint8_t i;
spi_start();
spi_write_byte(addr);
for (i = 0; i < len; i++){
*((data + i)) = spi_read_byte();
}
spi_stop();
}
void spi_write(uint8_t addr , uint8_t *data, uint8_t len)
{
uint8_t i;
spi_start();
spi_write_byte((0x80|addr));
for (i = 0; i < len; i++){
spi_write_byte(*(data + i));
}
spi_stop();
}
int main(void){
int i;
char buf[50] = {'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j'};
spi_setup();
spi_start();
for (i = 0; i < 10; i++)
buf[i] = spi_transfer(buf[i]);
spi_stop();
return 0;
}
static void sd_read_block(uint32_t block, uint8_t *buf)
{
int32_t i;
spi_start();
while (sd_command(READ_SINGLE_BLOCK, block) != 0x00);
while (spi_sendrecv(0xff) != 0xfe);
for (i = 0; i < 512; i++)
buf[i] = spi_sendrecv(0xff);
spi_sendrecv(0xff);
spi_sendrecv(0xff);
spi_stop();
}
static void sd_init(void)
{
int32_t i;
spi_setup(SPI_CS0, 0);
for (i = 0; i < 10; i++)
spi_sendrecv(0xff);
spi_start();
while (sd_command(GO_IDLE_STATE, 0) != 0x01);
while (sd_command(SEND_IF_COND, 0x000001AA) != 0x01);
while (sd_command(APP_CMD, 0) && sd_command(SD_SEND_OP_COND, 0x40000000));
while (sd_command(READ_OCR, 0) != 0x00);
spi_stop();
}
void spi_tx_word(uint8_t addr, uint16_t w)
{
uint8_t i;
spi_start();
spi_write_byte((0x80|addr));//send addr
for (i = 0; i< 16; i++){
if (w & 0x8000) {
spi_tx_bit(1);
}
else {
spi_tx_bit(0);
}
w <<= 1;
}
spi_stop();
}
uint16_t spi_rx_word(uint8_t addr)
{
uint8_t i;
uint16_t w = 0;
uint8_t spi_bit;
spi_start();
spi_write_byte(addr);// send addr
for (i = 0; i< 16; i++){
spi_rx_bit(spi_bit);
w <<= 1;
if (spi_bit)
w |= 1;
}
spi_stop();
return w;
}
int change_variable(void *p, values_t variance, var_bound vlue_bound, uint32_t prev_val)
{
int set_failed = 1;
int i;
#if defined (RS_ENABLED)
USART6_stop();
#elif defined (SPI_ENABLED)
spi_stop();
#endif
//Check variables for validity
if (variance == discrete){
if (vlue_bound.boundary != NULL){
for (i = 0; i < vlue_bound.num_el; i++){
if (vlue_bound.boundary[i] == *(uint32_t*)p)
break;
}
if (i < vlue_bound.num_el)
set_failed = 0;
}
}
if (variance == min_max){
if (vlue_bound.boundary != NULL){
if( *(uint32_t*)p >= vlue_bound.boundary[0] && *(uint32_t*)p <= vlue_bound.boundary[1])
set_failed = 0;
}
}
if (variance == any)
set_failed = 0;
if (set_failed){
//restore previous value
*(uint32_t*)p = prev_val;
conf_periph_init();
return 1;
}
//call interfaces init with new config
conf_periph_init();
return 0;
}
void
spi_hw_init_master(const spi_bus_t spi_num) {
/* Clear lock variable */
spi_lock[spi_num] = 0;
/* Block access to the bus */
spi_acquire_bus(spi_num);
/* enable clock gate */
spi_start(spi_num);
/* Clear MDIS to enable the module. */
BITBAND_REG(SPI[spi_num]->MCR, SPI_MCR_MDIS_SHIFT) = 0;
/* Enable master mode, select chip select signal polarity */
/* XXX: Hard-coded chip select active low */
/* Disable FIFOs, this can be improved in the future */
SPI[spi_num]->MCR = SPI_MCR_MSTR_MASK | SPI_MCR_PCSIS(0x1F) | SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK;
/* Enable interrupts for TCF flag */
BITBAND_REG(SPI[spi_num]->RSER, SPI_RSER_TCF_RE_SHIFT) = 1;
switch(spi_num) {
case SPI_0:
NVIC_EnableIRQ(SPI0_IRQn);
break;
case SPI_1:
NVIC_EnableIRQ(SPI1_IRQn);
break;
case SPI_2:
NVIC_EnableIRQ(SPI2_IRQn);
break;
}
/* disable clock gate */
spi_stop(spi_num);
/* Allow access to the bus */
spi_release_bus(spi_num);
}
void spi_init(void)
{
spi_stop();
spi_clk_l();
}
